Hi, I'm curious to know in what fashion bus cycles should be implemented in VHDL, specifically using the WISHBONE bus system. Describing these cycles behaviorally (wait statements) seems to be the logical solution, however the code would not be synthesizable (or would it be with newer tools?, if so which ones?). Likewise, how would one deal with timing issues (setup time/hold time) when dealing with this problem. Is the solution to these above two problems simply to write tedious state machines (mealy or moore?) and counters (for the timing), or is there hopefully a more efficient way? Can anyone suggest some references? Thanks in advance! Edmond _______________________________ Do you Yahoo!? Win 1 of 4,000 free domain names from Yahoo! Enter now. http://promotions.yahoo.com/goldrush

Hello: You have answer the question yourself. It depends the level of abstraction you use. If you describe at RT level you have to use the tedious state machines. The other solution is to use the wait statements and describe it at a behavioral level, there are many tools in the market that synthesize this behavioral description. I think is not a good solution. I don't know any other solution, is somebody know it, I am also interested. Regards Javier Castillo jcastillo at opensocdesign.com www.opensocdesign.com -----Mensaje original----- De: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] En nombre de Edmond Cote Enviado el: martes, 31 de agosto de 2004 14:35 Para: cores at opencores.org; socbuilder at opencores.org Asunto: [oc] VHDL bus cycle implementation for wishbone/opencores Hi, I'm curious to know in what fashion bus cycles should be implemented in VHDL, specifically using the WISHBONE bus system. Describing these cycles behaviorally (wait statements) seems to be the logical solution, however the code would not be synthesizable (or would it be with newer tools?, if so which ones?). Likewise, how would one deal with timing issues (setup time/hold time) when dealing with this problem. Is the solution to these above two problems simply to write tedious state machines (mealy or moore?) and counters (for the timing), or is there hopefully a more efficient way? Can anyone suggest some references? Thanks in advance! Edmond _______________________________ Do you Yahoo!? Win 1 of 4,000 free domain names from Yahoo! Enter now. http://promotions.yahoo.com/goldrush _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Hi, With regards to tools then, currently I have access to either standard Xilinx tools (XST, which clearly? does not support behavioral synthesis) or Synopsys V2001.08 and FPGA Compiler II. I have some reservations using Synopsys tools though. My impression of Synopsys' FPGA support was for ASIC prototyping only and hence need for very large FPGAs. Exactly how effective is Synopsys's at optimizing and instantiating logic for Xilinx devices?, have these concerns been addressed in newer releases of the tools? An alternative solution might be to use the vhdl output from bc_shell and copy those files to my Windows environment, not exactly an ideal solution. How do Leonardo or Synplify fit into the scheme of things? Thanks everyone, Edmond --- Javier Castillo jcastillo at escet.urjc.es> wrote: __________________________________ Do you Yahoo!? Yahoo! Mail - 50x more storage than other providers! http://promotions.yahoo.com/new_mail

Hello: All the synthesis tools gives very similar results. Xilinx works with Synopsys and Altera works with Mentor. Leonardo and Synplicity don't offer behavioral synthesis AFAIK, just RT. Synopsys Behavioral Compiler, generates a RT equivalent description so the synthesis flow from there is the same, just take the RT description, synthesize it, take the edf file and finish the process with XST tools. Regards Javier Castillo jcastillo at opensocdesign.com www.opensocdesign.com -----Mensaje original----- De: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] En nombre de Edmond Cote Enviado el: martes, 31 de agosto de 2004 17:14 Para: Discussion list about free open source IP cores Asunto: RE: [oc] VHDL bus cycle implementation for wishbone/opencores Hi, With regards to tools then, currently I have access to either standard Xilinx tools (XST, which clearly? does not support behavioral synthesis) or Synopsys V2001.08 and FPGA Compiler II. I have some reservations using Synopsys tools though. My impression of Synopsys' FPGA support was for ASIC prototyping only and hence need for very large FPGAs. Exactly how effective is Synopsys's at optimizing and instantiating logic for Xilinx devices?, have these concerns been addressed in newer releases of the tools? An alternative solution might be to use the vhdl output from bc_shell and copy those files to my Windows environment, not exactly an ideal solution. How do Leonardo or Synplify fit into the scheme of things? Thanks everyone, Edmond --- Javier Castillo jcastillo at escet.urjc.es> wrote: __________________________________ Do you Yahoo!? Yahoo! Mail - 50x more storage than other providers! http://promotions.yahoo.com/new_mail _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Hi Edmond,

I'm new to this myself, but you can find examples of how to
implement Wishbone cycles in VHDL in some of the VHDL cores
on the OpenCores website, e.g. the I2C controller.
I don't think there is an official reference on how to implement
Wishbone cores in VHDL.

This is the approach I've been using, with a very simple toy
example below:
process(wb_rst_i, wb_clk_i, wb_cyc_i, wb_stb_i) type state_type is { idle, reading, done); variable state : state_type; begin if (wb_rst_i = '1') then state := idle; elsif (rising_edge(wb_clk_i)) then case (state) => when idle => if (wb_cyc_i = '1') then state := reading; end if; when reading => wb_ack_o null; end case; end if; end process;
I'm not sure what you think is messy about the behavioural state-machine
approach; it seems straightforward to me.
The tool I use (Altera's Quartus) runs a timing-analyzer after synthesis
and warns me whenever timing requirements aren't met and shows the
critical paths. So I can either clock the circuit slower or cut the path
with registers.

But I am also a beginner, so maybe something about the above is bad
practise, and other VHDL gurus can speak up and correct me.

Hope this helps,
Paul

Edmond Cote wrote: