Hi:

I know this may not be right forum to ask help on Xilinx ISE tool but
some people here would be definitely using it. I have some issue with
running ISE in Modular Design mode. Basically what I want is a flow by
which I can manually place and route modules before generating their PIMs.
What I am doing till now:
- Run Active module Implementation till place and route to generate top.ncd.
- Use top.ncd in floorplanner to change the placement manually (after
using constrain from placement option) and write the constraints to ucf
file (I might be doing something wrong here !!!)
- After that when I do ngdbuild and map again, I get fatal error in map
phase.

Hope to get some help as I am really stuck.

Thanks
Praveen Durga
University of Bath, UK