Hi all,

It's my understanding that Wishbone was deliberately made simple by not
handling things like pipelined reads explicitly.

The example in the B.3 specification says that for synchronous memories
with a one-cycle read delay, all that is needed is an extra flip-flop on
the ack signal.

This works fine for single read cycles. For block read cycles, it
takes two cycles per address, as described in the Registered Feedback
chapter. The Cycle Type Identifier (CTI) signal "seems" to solve this
problem for bursts, but the fact that either the master or the slave can
insert wait states means that some data will be lost when the master
inserts a wait state. My question is, what's the preferred solution to
a pipelined memory slave?

In the ASCII waveform below, assume that a master is reading from a
memory slave with ack is the delayed stb by one cycle, and where data
0x00 is stored at address 0x00,
data 0x01 is stored at address 0x01, and so on.

____1|____2|____3| 4| ___5|____6|
WB_STB_O / \_____/

WB_ADR_O 0x00 0x00 0x01 xxxx 0x02 0x02

WB_DAT_I 0x00 0x00 0x01 xxxx 0x02
_________________ _____
WB_ACK_I _______/ \_____/

Edge 1: the master can't change it's address b/c it doesn't know
whether the slave will insert another wait state.
Edge 2: Master sample's ack, latches onto data 0x00, and presents
address 0x01.
Edge 3: Slave ack is delayed from Edge 2 stb, but master latches in
0x00 as the data at 0x01. Now assume the master only needs
two bytes before inserting a wait state.
Edge 4: The slave presents the data at 0x01 before it realises that
the master has stalled. Master presents some undefined address.
Edge 5: Slave presents the data at the undefined address, master raises
stb again. Lather, rinse, repeat.

There seems to be several solutions:

1) If stb goes low, raise ack asynchronously with it for the
first cycle only, when it rises again. This is a second
signal which is OR'd with the memory ack.
2) Internally precache the slave's data so that stb never needs
to go low.
3) Ensure that an end-of-burst lasts for two cycles with the same
address (or however long it takes for the memory slave to ack).

It's possible I've misunderstood the situation and made it more
complicated than it actually is. If you've read this far and can clear
this up for me, I would greatly appreciate it. It also seems this would
be useful for other people using Wishbone with pipelined memories.

Thanks in advance,
Paul

Are you talking about a true pipelined bus, like AMBA or CoreConnect, or a
wishbone bus?


No, the master can't change it's address because ACK is negated.



No, for Registered Feedback cycles, the master's STB_O and the slaves ACK_O
are generated independantly. So a transfer is valid when CYC is asserted,
STB is asserted, and ACK is asserted. Both the master and the slave need to
check these three signals.

In your case edge3 means:
- Master is ready to transfer 1 more cycle
- Slave is ready to transfer 1 more cycle
- CYC is asserted (not shown), STB is asserted, and ACK is asserted => valid
transfer.

However the slave should present the data for address 0x01. Even though it
hasn't seen the actual address yet, it knows what to expect. The CTI and CTE
signals inform the slave what kind of burst the master requires. In this
example a linear burst.


Cheers,
Richard

Richard Herveille wrote:


Can't a Wishbone bus implement a pipeline using a burst and
registered feedback?



No, the master can't change it's address because ACK is negated.

Not really. With true pipelined busses there's an address phase and a data
phase. These phases are in different time slots (bus cycles). As a matter of
fact they don't even have to be time correlated, although the data phase is
always after the address phase of course.



A Registered Feedback capable slave only uses the address during the initial
phase. After that it should update the addresses internally, based on
CYC/STB/ACK, and CTI/CTE.

Note that a slave does not have to support CTI/CTE or may support a subset
of burst cycles. In that case it needs the addresses generated by the
master. In those cases the cycles are treated as being Classic Wishbone
cycles, with the implied additional cycle penalty.

Richard