Hi all, I want to inform you about the upcoming event FPGA world conference 23 september 2004 in Vasteras Sweden. For information see http://fpgaworld.com/conference/ I am going to talk about the exciting subject: OpenCores - free open source IP cores, recent cores and future development My intention is to talk about: recent work on OR1200 (qmem,Structured ASIC,..) a new core I am working on making it possible to configure and boot an OpenRISC system implemented in an ALTERA Cyclone device from a standard SPI FLASH memory. When the system is up the memory content can be written making it possible to have internet connected designs to update their own hard and software. I need some input on other new cores. Also some input on functions that are planned to be implemented in cores, OpenRISC and others. When one look at all the projects available at opencores it looks very impressive. The OR1200 is a competent processor and all wishbone compliant peripherals makes system design with open source cores possible. What I believe is missing is a tool to handle that system in a convenient way. I have written a wishbone generator, Wishbone builder, that generates HDL for the system bus. This makes it easier to have a design where you can add cores rather easy. Any plans for a system generator (like the SoPC builder from ALTERA) for opencores ?? All inputs are welcome regards /Michael Unneback