Hi,

I have used the 16750 core in a Cyclone-III implementation (no CPU, not wrapping the interface).

Baud rate and transmit side has tested fine in hardware. But the receiver has an issue. When it is fed with a valid serial stream the receiver (uart_receiver.vhd) generates a framing error rather than RXfinished. Any body seen the problem, fixed it?



The image is the Signal Tap analyser results of the test.

John

hi
i am manjunath here, can any one please tell me the frquencies of
the clk and BR_clk used in 16550 UART. As early as possible.


thanks and regards
manju