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PROG_B pin low pulse period

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PROG_B pin low pulse period by Unknown on Sep 2, 2004			Not available!
Hi, What should be the PROGRAM pin's low pulse timing to initiate xilinx spartan FPGA configuration. Thanks Dipak. Hi, What should be the PROGRAM pin's low pulse timing to initiate xilinx spartan FPGA configuration. Thanks Dipak.

PROG_B pin low pulse period by Unknown on Sep 2, 2004			Not available!
Hi, In the data sheet it is written that the low going pulse on PROG_B pin only require while you need reconfiguration without power-up cycle. So in my case I want configure the FPGA only at power-up. In this case I won't be using this pin. So what to do with this pin? tie HIGH/LOW? Thanks, Dipak. Victor Snesarev wrote: [q]Dipak, You can find this in DC and Switching Characteristic section of Xilinx datasheets. For several of their families the minimum width is 300ns. --- Dipak Modi <<A HREF="http://www.opencores.org/mailman/listinfo/cores">dipakm at einfochips.com</A>> wrote: [q]Hi, What should be the PROGRAM pin's low pulse timing to initiate xilinx spartan FPGA configuration. Thanks Dipak. _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] [/q] Hi, In the data sheet it is written that the low going pulse on PROG_B pin only require while you need reconfiguration without power-up cycle. So in my case I want configure the FPGA only at power-up. In this case I won't be using this pin. So what to do with this pin? tie HIGH/LOW? Thanks, Dipak. Victor Snesarev wrote: Dipak, You can find this in DC and Switching Characteristic section of Xilinx datasheets. For several of their families the minimum width is 300ns. --- Dipak Modi dipakm at einfochips.com> wrote: Hi, What should be the PROGRAM pin's low pulse timing to initiate xilinx spartan FPGA configuration. Thanks Dipak. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

PROG_B pin low pulse period by Unknown on Sep 2, 2004			Not available!
Since the PROG_B going low triggers an FPGA reconfiguration, then put a pull-up resistor on that line if it will not be tied to anything. Here's what the datasheet says: "PROG_B Input Active Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up resistor." -Victor --- Dipak Modi <<A HREF="http://www.opencores.org/mailman/listinfo/cores">dipakm at einfochips.com</A>> wrote: [q] Hi, In the data sheet it is written that the low going pulse on PROG_B pin only require while you need reconfiguration without power-up cycle. So in my case I want configure the FPGA only at power-up. In this case I won't be using this pin. So what to do with this pin? tie HIGH/LOW? Thanks, Dipak. Victor Snesarev wrote: [q]>Dipak, > >You can find this in DC and Switching Characteristic section of Xilinx >datasheets. For several of their families the minimum width is 300ns. > > > >--- Dipak Modi <<A HREF="http://www.opencores.org/mailman/listinfo/cores">dipakm at einfochips.com</A>> wrote: > > > [q]>Hi, > >What should be the PROGRAM pin's low pulse timing to initiate xilinx >spartan FPGA configuration. > >Thanks > >Dipak. > >_______________________________________________ ><A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> > > >[/q] > > > > >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] Since the PROG_B going low triggers an FPGA reconfiguration, then put a pull-up resistor on that line if it will not be tied to anything. Here's what the datasheet says: "PROG_B Input Active Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up resistor." -Victor --- Dipak Modi dipakm at einfochips.com> wrote: Hi, In the data sheet it is written that the low going pulse on PROG_B pin only require while you need reconfiguration without power-up cycle. So in my case I want configure the FPGA only at power-up. In this case I won't be using this pin. So what to do with this pin? tie HIGH/LOW? Thanks, Dipak. Victor Snesarev wrote: >Dipak, > >You can find this in DC and Switching Characteristic section of Xilinx >datasheets. For several of their families the minimum width is 300ns. > > > >--- Dipak Modi dipakm at einfochips.com> wrote: > > > >Hi, > >What should be the PROGRAM pin's low pulse timing to initiate xilinx >spartan FPGA configuration. > >Thanks > >Dipak. > >_______________________________________________ >http://www.opencores.org/mailman/listinfo/cores > > > > > > > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

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