-----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org]On Behalf Of carol198 at tiscali.es Sent: 6. september 2004 12:46 To: cores at opencores.org Subject: [oc] ETHERNET MAC 10/100Mbps TEST BENCH Hi, I write to this forum to ask a question about the Ethernert Mac 10/100Mbps core. First of all, in the test-bench tb_ethernet.v I think there might be an error in the inputs of the wb_bus_mon: the slave bus monitor receives the TAG_O from the master (all the other signals are the slave's) and the master receives the slave's TAG_O. This causes errors that are displayed during the simulation. This is solved by replacing the signals from the master by the slave's and vice-versa. The second problem I have founded is a little more complicated. In the simulation of the test bench, I get the following error transcript MAC HALF DUPLEX FLOW TEST # Time: 876116327 # TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) # ->TX Defer occured # ->IPGR2 timing checking # Time: 876264399 # *E TX buffer descriptor status is not correct: 5800 instead of 5802 # ->TX Defer occured I have founded that the buffer description status comes from the signal /eth_top/eth_macstatus/DeferLatched this signal should be set to 1 when a Deferred Transmission occurs. actually, it is the AND of two signals that get asserted in different states /et_top/eth_txethmac/eth_txstatem/ StateIdle and StateData, so it is normal that this signal is never asserted! and more... # Time: 877635687 # *E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision # ->IPGR2 timing checking # Time: 877826379 # *E Wrong data of the transmitted packet # ->TX Defer occured Can someone give me an explanation of all these? Regards, Caroline Luengo _______________________________________________ http://www.opencores.org/mailman/listinfo/cores