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J. Everett by jeverett on Oct 2, 2010			jeverett Posts: 4 Joined: Jun 27, 2009 Last seen: Jun 19, 2017
Is there any interest in a core that connects the wishbone Bus to Xilinx MIG(memory interface generator) logic? I have began developing this to access the DDR3 RAM on a Xilinx SP605 Spartan 6 board. Jody Everett Is there any interest in a core that connects the wishbone Bus to Xilinx MIG(memory interface generator) logic? I have began developing this to access the DDR3 RAM on a Xilinx SP605 Spartan 6 board. Jody Everett

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