Hello, I am a newbie in this embedded system field and was first time exposed to vhdl. However, i am familiar with C programming. For the past month i'm doing this literature review on PLB Bus Master IP Core. And right now i have started doing a simple mini project on "BRAM to VGA Burst Bus Master". This are the sequence of the program:

1. MicroBlaze processor writes color data (RBG) to BRAM(slave core). [done]
2. Then it will write a flag to another location on the BRAM. [done]
3. In the meantime, the master soft core will repeatedly read the BRAM to check the flag.
4. If the flag is set, master core will read the all the data that previously written by the processor.
5. Upon completion, the master core will write the data to a VGA moniotr to display the color.

I'm using Spartan3e starter kit, EDK 10.1. I've created my custom ip core, and now in the stage of modifying the vhdl code. There are 5 state machine (provided by Xilinx as a reference purpose) need to be translated. This is for sequence #3 and #4 as above. I can do slave read and write initiation, but i didn't understand how to do the master initiation and i'm a bit weak on the state machine coding. Can anyone help me?

Mia.

Well yes, I can help you with the VHDL coding of the state machine!

But in order to do that I need to understand what needs to be done exactly, maybe from scratch.

So you can send me whatever documents, motivation, help-files you have to this ID, while at the same time explaining me the process of work flow.

debayan_p@rediffmail.com

Also you must understand that I have my own work to do, and cannot devote full time for your work!

Cheers,
Debayan

Hello Debayan,

Thank you for your reply. Appreciate your help. Sorry for the late response as i was just finished my final exam last week. Right now continue with my master ip core project. Will email you shortly.

Thank you.
Mia.