Hello everyone!

Im a student working on an embedded linux design based on Xilinx MicroBlaze on Virtex-II Pro board. I want to use the AC'97 controller to play sounds connecting speakers to the sound line out line built in the development platform. I have successfully added the plb46_wb bridge to my desing but I keep failing to add the AC 97 controller. I'm using the 'Create / Import Peripheral Wizard' to create a new peripheral using the verilog files provided in the Ac'97 developed here. Am I doing it right? And if so, how do I connect the ports correctly? I keep getting an ' WB_RTY_I port is driven by a sourceless connector" error.

Can anyone help me? thanks in advance

Antonio Garcia

Since you are using Microblaze, maybe you should post your question to Xilinx's forums.

Since I'm using both the plb_wb bridge and the ac97 controller developed here , I thought this is a suitable place for asking my questions. Anyways thanks for your advice and I'll post my question on xilinx forums too.

Antonio Garcia.

Did I understand you right, that you have an AC'97 and plb46_wb IP core from opencores.org?
And you want to use them with Xilinx XPS?

Yes, that's what I mean. I got both them from opencores.org. The plb46_wb Ip core includes both .mpd and .pao files so it appears available in Xilinx XPS in "Project Local pcores"-->"Bus and Bridge". I have added it to my design and successfully connected it to the mb_plb bus. Then I made a "New connection" for each port of the plb46_wb instance.

As for the ac'97 core only the verilog files are provided so I tried to use them to "Add a new peripheral" to my project and that's the point were I'm stuck. I pointed to the ac97_top.v file as top file for the new item and the wizard managed to create the ac97_top_1.00 ip core. Then I added it to the design but I can't connect the ports right. I have connected the 8 matching ones, leaving disconnected ones unmatching, ones for DMA and ones for power management. What am I doing wrong? I'm quite new to FPGA design so excuse me if some of the things I say just don't make sense.

I don't know both IP cores, but I think the easiest way is to add the whole AC'97 core to the plb46_wb core, that everything appears to XPS as one core.
If you try this approach, you need to connect the plb46_wb master interface to the ac'97 slave interface manually and you may adapt data/plbv46_2_wb_v2_1_0.pao (see [1] more more information)

A more difficult approach is to add and define a new bus (the Wishbone Bus with arbiter in this case). I did this successful when I wrote the PLB-to-WB Bridge [2].
Have a look at some Xilinx *.mpd files (like [3]) to understand, how this works.
With such a mpd file, XPS knows how to connect slaves and masters to the bus and auto-generates the necessary files. You may find useful information in [1], too.



[1] http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/psf_rm.pdf
[2] http://www.opencores.org/ocsvn/plb2wbbridge/plb2wbbridge/trunk/systems/EDK_Libs/WishboneIPLib/pcores/wb_conbus_v1_00_a/
[3] XILIX_ROOT/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/data/plb_v46_v2_1_0.mpd