Hello,

I wanted to discuss an interesting idea to develop open cores. http://www.c-to-verilog.com provide free access to their C-to-verilog compiler. They allow translation of regular C code into Verilog for FPGAs. It creates cores which are simple for embeding in other projects.

What do you guys think ?

Hi,

I have not ever use the c-to-verilog service, I am interested in it:)
However, I still requires a tool that supports us to modify current version of C/Verilog code in order to produce subversion of it. For example tool with architecture description language (ADL) aoutomatically generates instruction set simulator, compiler, and HDL templates. The ADL ristricts of coding the architecture, however, it can shows/provides unified viewpoint across the versions and so on.

The simple translation might be first step, I requires quality of translation that can generates verilog code I expected.

Hi Nadav,

It's a nice idea, but a more than a decade of work in this field has only yielded limited success. Celoxica sunk $100m+ without success into trying to convert software languages (in their case Handel-C, which was easier to translate than C) into hardware. Forte Design Systems have been at it for nearly as long, and have some success, but you have to write in transactional SystemC and you need to guide the conversion system with additional rules. Bluespec have a similar approach. Companies like Critical Blue focus on automating just specialist co-processor functions.

At the research level, take a look at the work of David Greaves (http://www.cl.cam.ac.uk/~djg11/) and Krste Asanovic (http://www.eecs.berkeley.edu/~krste/). There are many research groups investigating this area around the world.

Tools like www.c-to-verilog.com appear from time to time. They can generally do a reasonable job of converting small fragments of C into Verilog, but nothing better than a competent hardware engineer would write in an hour or two. Dealing with small fragments is not the real problem - that's what IP libraries are for. It is the big design issues that are the problem, and C-to-Verilog can't help you there.

As an example I gave www.c-to-verilog.com the UART code from Or1ksim, to see how good a UART it would generate. An example of a typical small peripheral. But even that is too big for them. I got a small Verilog file, with a module called "_Z28err_src_file_is_way_too_longv". It seems that even something as modest as this is too much. I then tried the Or1ksim 32-bit CRC code (4 small functions of 5 lines or less). When I finally got the C into a form that their tool would accept (there are quite a lot of restrictions), it generated an empty Verilog file.

The problem is that C is fundamentally serial and Verilog is fundamentally parallel. All the research is about how you automatically deduce timing information and parallelism from a serial input. As an example consider how an automated system would automatically deduce that a hash table in C should be implemented as an associative memory in Verilog. Hence the use of SystemC (which gives you some suggestions of the parallelism) and the need for additional input (to suggest what to do about timing information). You'll see that even for the simple examples in www.c-to-verilog.com you have to give guidance in 8 different areas.

So I remain a sceptic that this will help you generate a new core. The technology can help in some areas, but to get good results you'll still need a lot of top quality hardware engineering work.

ATB,


Jeremy