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RE: NEWS-FLASH: Free VHDL to Verilog Translator
by ejong69 on May 26, 2018 |
ejong69
Posts: 1 Joined: Sep 10, 2014 Last seen: Mar 27, 2024 |
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### Edited by OC-admin
Stepped over the same problem.
Need to edit manually the vhdl2vl.y file.
Here is my edited file.
Regards,
Daniel
------------------------------------------------------------------------
----- Original Message -----
From: yanzhang1999 at h...
To: cores at o...
Date: Mon, 21 Apr 2003 06:39:04 -0100
Subject: Re: [oc] NEWS-FLASH: Free VHDL to Verilog Translator
Hi, All,
I could not successfully compile the vhd2vl program for windows. I
got
source file from following link,
http://www.ocean-logic..com/pub/vhd2vl.tgz
I build cygwin and gcc, bison and flex in my w2k, but the gcc found
a
lot of format error.
Would someone help me?
Besides, could any one tell me how to make executable in cygwin.
The
make install file have to use some "make".
Thanks!
Yan
----- Original Message -----
From: Rudolf Usselmann rudi at a... >
To: OpenCores Mailing List cores at o... >
Date: Sat, 21 Sep 2002 20:09:47 +0700
Subject: [oc] NEWS-FLASH: Free VHDL to Verilog Translator
>
>
>
> I don't know if you guys have seen this but there is a free
> VHDL to Verilog translation tool that was mentioned in a
> recent EEtimes article.
>
> This is the EEtimes article:
> http://www.eetasia.com/ART_8800272174_499481,499482.HTM
>
> This is the company offering it (download page):
> at www.ocean-logic.com/downloads.htm
>
> Regards,
> rudi
>
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RE: NEWS-FLASH: Free VHDL to Verilog Translator
by ocadmin on May 31, 2018 |
ocadmin
Posts: 76 Joined: Oct 27, 2007 Last seen: Apr 19, 2024 |
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please avoid posting long code snippets on the forum.
Use the attach file feature if you want to share code with others. Best, /:/ OC-team |
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RE: NEWS-FLASH: Free VHDL to Verilog Translator
by inflector on May 31, 2018 |
inflector
Posts: 6 Joined: Aug 28, 2017 Last seen: May 31, 2018 |
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I don't think that is a thread I think you are looking at someone trying to social engineer here.
All the posts are the same. The link to the article doesn't work. The other one is an executable. I'd delete this thread and ban the user's IP if they won't respond to a simple query explaining why my assessment is wrong. |
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RE: NEWS-FLASH: Free VHDL to Verilog Translator
by aikijw on Jun 1, 2018 |
aikijw
Posts: 76 Joined: Oct 21, 2011 Last seen: Jul 8, 2023 |
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I think you might be just a little paranoid...
I'm not the OP, but if you do the following: 1) Remove the obvious extra dot in the URL... 2) Manually rewrite the https: protocol tag in the URL to "http" (which I think is a well known OpenCores feature) you'll be able to download the file vhd2vl.tgz, which is not an executable... It's a tarball... The tarball does, indeed, contain the source code for an attempt to translate from VHDL to Verilog... I make no claim that it compiles, or *if* it does, it is actually successful at what it does... If you read the readme file (found in the tarball), the author seems sincere in his attempt to build a translator. I'm not sure that I, personally, see much utility in such a tool, but... There you have it... :-)
I don't think that is a thread I think you are looking at someone trying to social engineer here.
All the posts are the same. The link to the article doesn't work. The other one is an executable. I'd delete this thread and ban the user's IP if they won't respond to a simple query explaining why my assessment is wrong. |
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RE: NEWS-FLASH: Free VHDL to Verilog Translator
by hno on Jul 12, 2018 |
hno
Posts: 7 Joined: Dec 17, 2012 Last seen: Oct 4, 2021 |
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A more up to date version is maintained at http://doolittle.icarus.com/~larry/vhd2vl/ ( source repo at https://github.com/pliu6/vhd2vl )
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RE: NEWS-FLASH: Free VHDL to Verilog Translator
by AdoraKalb on Aug 10, 2018 |
AdoraKalb
Posts: 1 Joined: Aug 9, 2018 Last seen: Sep 7, 2018 |
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Hi...i am a new user here. As per my knowledge It really depends on the reason for the conversion. Most modern EDA tools will accept both and even combinations of the two in the same design. A quick and dirty route would be to use a synthesis tool such as Synopsys to convert the VHDL to "generic" logic and then use a TCL or Perl script to replace the generic logic with Verilog primitives.
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