Hi everyone,
after some struggles I have eventually found the time to revive an old project on opencores which hasn't been updated since a while:

a spacewire link and router.

I have just been assigned as co-maintainer since the original one seems not available since a while.
I intend to bring back the status of the project to "planning", since I would like to discuss again the structure of the project, starting from the specification documentation and the overall design structure.

I'd like to stress that I am not a spacewire expert, but I have been working on a "modified" version of it that is in use in the AMS-02 experiment (http://ams.cern.ch) which is ready to be launched next year on the International Space Station.

At the moment I would like to share my motivation, hoping to find some feedback and some interest.

The purpose of the spacewire standard is (citation from the ECSS�E�ST�50�12C):

- to facilitate the construction of high�performance on�board data�handling systems;
- to help reduce system integration costs;
- to promote compatibility between data�handling equipment and subsystems;
- to encourage reuse of data�handling equipment across several different
missions.

In this respect a handful of firms have grown to provide SoC know-how and system integration capabilities to "serve" space exploration and space science. ESA for example is promoting R&D in order to improve european space industry sector.
Even though I do understand the commercial impact of this approach, I still believe that we can do much more through an open platform, improving the quality of the solutions and allowing for a greater spectrum of products.
In my limited experience I have been working on two space experiments (pamela.roma2.infn.it and ams.cern.ch) and witnessed other four at least (ALTEA, GLAST-FERMI, LAZIO-SiRAD, AGILE). A great deal of development was focused on the onboard data-handling systems, with ad-hoc interfaces and non-standard solutions.
We had the possibility to adopt spacewire, but the "closed" solutions provided by the industry is rather counter productive in an open environment like the one of the academic collaborations we have (costs are rather high and liability is often unclear).
This is where open IP cores may come in action and empower low-budget experiments to build reliable and reusable systems cutting the development costs and enabling them to focus on science.
The industry itself may benefit from this approach, since a good licensing policy (like the LGPL) may foster interests and wide spread the usage (hence enhancing the reliability) of these IP cores.

A more reliable and widely used standard gives a tremendous boost to our space related dreams and even though it's just a piece of wire, I believe it still build bridges worldwide.

Any feedback is appreciated.

Al

p.s.: this post will be on comp.arch.fpga, comp.lang.vhdl, comp.lang.verilog as well

Hi Al,

I m not an expert in space wire either, but I would like to help. I am very proficient in VHDL and Verilog.


Regards,

Ivan

Hi Ivan, appreciate your interest. Please send me an email (check it on the project page) and we may get organized on how to proceed.

Al