hi to all,
i want usart core for synchronous interfacing .... i have found many cores with asynchronous interface
regards

I see two questions to be answered:

1. For a synchronous interface, a clock must be generated, either synthesized from the encoded data stream itself (e.g., with a PLL), or transmitted separately from the data. If the clock generating
circuit should be part of your design, it is necessary to specify how the data is encoded.

2. Is the intended clock frequency low enough, so that the clock could be sampled with the FPGA's clock? If not, you will have different clock domains, requiring a data buffer that can be accessed from both domains.

Regards,
Hellwig