what is the best adder and multiplier to design a neuron with fxed point data to reduce area an time delay??

Use MAC blocks, or MUL blocks (plus an adder implemented in CLBs) if you are doing an FPGA implementation and your device incorporates such blocks.

That will depend on the underlying architecture you are using to implement the evaluation of the network. Direct dedicated parallel processing, i.e., synthesizing each neuron as dedicated hardware can deplete the resources of any FPGA for even a small network.

You can use local sharing of resources for a number of neurons, having a matrix of processing cells that use a fast MAC structure to evaluate the responses of the cell members. If the targeted FPGA has dedicated MAC blocks, you can build the local neuron descriptors as a data structure and circulate the inputs and weights through the MAC core, having a pipelined micro-cycle to update all local nodes.

Hi, do you have the Verilog cords of the neural network? I'm studying that and want to realize how to code the cords. Many thanks!