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again:setup time,hold time,clock skew
by wjx197733 on Sep 18, 2004
wjx197733
Posts: 3
Joined: Jun 3, 2006
Last seen: Feb 10, 2012
What is the function of hold?why clock skew may result in hold time
violations if its bad enough?
IN a book,I find a word:the delay of combinal logic must be bigger than
the width of clock(i.e. the high level of clock) and must be less than the
period of clock.and why?

again:setup time,hold time,clock skew
by Unknown on Sep 19, 2004
Not available!
wjx197733 at emails.bjpu.edu.cn wrote:
What is the function of hold?why clock skew may result in hold time
violations if its bad enough?



There is a finite window where the data must be constant so the flipflop
can sample it
and get a known answer. Related to the design of the flipflop.

Ignoring issues like process spread/voltage/temp/accuracy for now, that
window starts at the setup time
(positive setup is before clock edge) and ends at the hold time
(positive hold after clock)

Thats hold.

Why is clock skew an issue? Think of 2 D-type flipflops A,B.
Wired as a shift register, so a direct connection from QA to DB.
In the simplest case , no clock skew, B will clock data correctly if
the clock-Q delay of A is
greater then B hold time.
Try some numbers, 0.25u , clock-Q might be 0.5ns, hold time 0ns. -
works with no skew.
Now let me add skew - arranged so that B clocks later than A by 0.6ns
(this is a sucky clock tree)
Because A clocks before B, the output of A changes when B is sampling
it. Violating hold.
You might get the first value, you might get the next value. If you are
really really unlucky - you may get a metastable.

In practice, you might see the shift register having its normal delay
for rising edge (slower) transitions
and a zero-cycle path for falling edges.

IN a book,I find a word:the delay of combinal logic must be bigger than the width of clock(i.e. the high level of clock) and must be less than the period of clock.and why? _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

I disagree with the first statement. for flipflops anyway. Has
application for latches.
The second statement is correct in general.
The path from one flop to the next should be less than a clock cycle or
you will violate setup on the
destination flop.
The logic will operate differently depending on the silicon process,
supply voltage, temperature, time of day,
noise local to the flop, which is in general bad.
Of course, if the logic design is such that there are actually several
cycles before the data is used, then its a multicycle path, which is a
different case, different rules.
john



I




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