Hi Friends I am currently doin my university project on the topic
Low Power AES algorithm using VHDL

this is the base paper im following
www.martes-itea.org/.../Hamalainen-Design_and_Implementation_2.pdf

Actually i got the cores from their website and was having a problem
in understanding it . I have attached the core also below.
They are using 8- bit data paths and i was having problems in
understanding their architecture and implementation in VHDl.

Currently i'm trying to understand the key expansion unit.
I figured out the operation of the mux controls but im having trouble
understanding the shift register process in the key expansion unit.
Also im having lil trouble trying to understand the loading and
unloading proces..
If someone could pls help me out it wud be a great help..


I have attached the cores below.

Thank you
Rejin