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memctrl by Unknown on Sep 28, 2004			Not available!
Hi All, I'd like to inqure have anybody used the memory controler which was coded by Rudolf Usselman? I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits? Thank you yours anwsers. Best regards: Erno Varga Hi All, I'd like to inqure have anybody used the memory controler which was coded by Rudolf Usselman? I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits? Thank you yours anwsers. Best regards: Erno Varga

memctrl by Unknown on Sep 29, 2004			Not available!
Dear All, So nobady use this module? Erno ----- Original Message ----- From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">verno at a...</A><<A HREF="http://www.opencores.org/mailman/listinfo/cores">verno at a...</A>> To: Date: Tue Sep 28 11:13:56 CEST 2004 Subject: [oc] memctrl [q] Hi All, I'd like to inqure have anybody used the memory controler which was coded by Rudolf Usselman? I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits? Thank you yours anwsers. Best regards: Erno Varga [/q] Dear All, So nobady use this module? Erno ----- Original Message ----- From: verno at a...verno at a...> To: Date: Tue Sep 28 11:13:56 CEST 2004 Subject: [oc] memctrl Hi All, I'd like to inqure have anybody used the memory controler which was coded by Rudolf Usselman? I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits? Thank you yours anwsers. Best regards: Erno Varga

memctrl by Unknown on Sep 29, 2004			Not available!
On Wed, 2004-09-29 at 17:11, <A HREF="http://www.opencores.org/mailman/listinfo/cores">verno at analogic-computers.com</A> wrote: [q] Dear All, So nobady use this module? Erno[/q] There are quite a few users of the Memory Controller including numerous commercial users ... But I think everybody is busy and has no time to provide free tech support ... rudi ============================================================= Rudolf Usselmann, ASICS World Services, <A HREF="http://www.asics.ws">http://www.asics.ws</A> Your Partner for IP Cores, Design, Verification and Synthesis On Wed, 2004-09-29 at 17:11, verno at analogic-computers.com wrote: Dear All, So nobady use this module? Erno There are quite a few users of the Memory Controller including numerous commercial users ... But I think everybody is busy and has no time to provide free tech support ... rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis

memctrl by Unknown on Oct 1, 2004			Not available!
Dear Rudi, Just one question, please anwser it isn't difficult and no time need the designer of the memctrl. I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits? Thank you yours anwsers. Best regards: Erno Varga ----- Original Message ----- From: Rudolf Usselmann<<A HREF="http://www.opencores.org/mailman/listinfo/cores">rudi at a...</A>> To: Date: Wed Sep 29 13:32:30 CEST 2004 Subject: [oc] memctrl [q] On Wed, 2004-09-29 at 17:11, <A HREF="http://www.opencores.org/mailman/listinfo/cores">verno at a...</A> wrote: [q]> Dear All, > > So nobady use this module? > > Erno [/q] There are quite a few users of the Memory Controller including numerous commercial users ... But I think everybody is busy and has no time to provide free tech support ... rudi [/q] ====================================================== ======= [q] Rudolf Usselmann, ASICS World Services, <A HREF="http://www.asics.ws">http://www.asics.ws</A> Your Partner for IP Cores, Design, Verification and Synthesis [/q] Dear Rudi, Just one question, please anwser it isn't difficult and no time need the designer of the memctrl. I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits? Thank you yours anwsers. Best regards: Erno Varga ----- Original Message ----- From: Rudolf Usselmannrudi at a...> To: Date: Wed Sep 29 13:32:30 CEST 2004 Subject: [oc] memctrl On Wed, 2004-09-29 at 17:11, verno at a... wrote: > Dear All, > > So nobady use this module? > > Erno There are quite a few users of the Memory Controller including numerous commercial users ... But I think everybody is busy and has no time to provide free tech support ... rudi ====================================================== ======= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis

memctrl by Unknown on Oct 1, 2004			Not available!
On Fri, 2004-10-01 at 14:03, <A HREF="http://www.opencores.org/mailman/listinfo/cores">verno at analogic-computers.com</A> wrote: [q] Dear Rudi, Just one question, please anwser it isn't difficult and no time need the designer of the memctrl. I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits?[/q] Erno, Yes thats how it is supposed to work. It will do two 16 bit reads to assemble one 32 bit word. I'm pretty sure I am covering that case in the test bench. Take a closer look how the memories are connected and the memory controller is programed. The memory controller must be properly programed so it is aware that it is talking to a 16 bit device. If you see only one access to the FLASH, than the memory controller thinks it's a 32 bit device (thats what I suspect, since you are getting all ones on the top ...). [q] Thank you yours anwsers. Best regards: Erno Varga[/q] Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, <A HREF="http://www.asics.ws">http://www.asics.ws</A> Your Partner for IP Cores, Design, Verification and Synthesis On Fri, 2004-10-01 at 14:03, verno at analogic-computers.com wrote: Dear Rudi, Just one question, please anwser it isn't difficult and no time need the designer of the memctrl. I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits? Erno, Yes thats how it is supposed to work. It will do two 16 bit reads to assemble one 32 bit word. I'm pretty sure I am covering that case in the test bench. Take a closer look how the memories are connected and the memory controller is programed. The memory controller must be properly programed so it is aware that it is talking to a 16 bit device. If you see only one access to the FLASH, than the memory controller thinks it's a 32 bit device (thats what I suspect, since you are getting all ones on the top ...). Thank you yours anwsers. Best regards: Erno Varga Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis

memctrl by Unknown on Oct 1, 2004			Not available!
Please adjust your clock: X-Mailer: Ximian Evolution 1.4.6 Date: Wed, 01 Oct 2003 14:43:03 +0700 rick Please adjust your clock: X-Mailer: Ximian Evolution 1.4.6 Date: Wed, 01 Oct 2003 14:43:03 +0700 rick

memctrl by bporcella on Oct 1, 2004			bporcella Posts: 22 Joined: Jan 16, 2004 Last seen: Oct 2, 2007
At 12:03 AM 10/1/2004, you wrote: [q]Dear Rudi, Just one question, please anwser it isn't difficult and no time need the designer of the memctrl.[/q] You know it doesn't bother me much when graduate students ask silly questions on this list.... seems like kind of par-for-the course. But an employee of analogic-computers.com ????? If you can't figure it out for yourself, perhaps you should hire somebody who can. Jeeze.... at least get the English readable. [q]I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits? Thank you yours anwsers. Best regards: Erno Varga ----- Original Message ----- From: Rudolf Usselmann<<A HREF="http://www.opencores.org/mailman/listinfo/cores">rudi at a...</A>> To: Date: Wed Sep 29 13:32:30 CEST 2004 Subject: [oc] memctrl [q]> On Wed, 2004-09-29 at 17:11, <A HREF="http://www.opencores.org/mailman/listinfo/cores">verno at a...</A> wrote: [q] > Dear All, > > So nobady use this module? > > Erno[/q] > There are quite a few users of the Memory Controller including > numerous > commercial users ... > But I think everybody is busy and has no time to provide free > tech support ... > rudi >[/q] ====================================================== ======= [q]> Rudolf Usselmann, ASICS World Services, <A HREF="http://www.asics.ws">http://www.asics.ws</A> > Your Partner for IP Cores, Design, Verification and Synthesis > >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] bj Porcella <A HREF="http://pages.sbcglobal.net/bporcella/">http://pages.sbcglobal.net/bporcella/</A> At 12:03 AM 10/1/2004, you wrote: Dear Rudi, Just one question, please anwser it isn't difficult and no time need the designer of the memctrl. You know it doesn't bother me much when graduate students ask silly questions on this list.... seems like kind of par-for-the course. But an employee of analogic-computers.com ????? If you can't figure it out for yourself, perhaps you should hire somebody who can. Jeeze.... at least get the English readable. I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits? Thank you yours anwsers. Best regards: Erno Varga ----- Original Message ----- From: Rudolf Usselmannrudi at a...> To: Date: Wed Sep 29 13:32:30 CEST 2004 Subject: [oc] memctrl > On Wed, 2004-09-29 at 17:11, verno at a... wrote: > Dear All, > > So nobady use this module? > > Erno > There are quite a few users of the Memory Controller including > numerous > commercial users ... > But I think everybody is busy and has no time to provide free > tech support ... > rudi > ====================================================== ======= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and Synthesis > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores bj Porcella http://pages.sbcglobal.net/bporcella/

memctrl by Unknown on Oct 1, 2004			Not available!
Erno: For single word reads, of course you can simply use the first 16 bits and ignore the rest of the bus. If you want to read bursts through a 16 bit bus, you will just need a 16 bit memory. In burst mode, the memory itself does the address increment, and the controller simply picks the data in sequence as it appears on the bus. Strictly speaking, you probably don't even need to change the memory controller, since it works on word addresses rather than byte addresses. Just write glue logic that reads the upper 16 bits of each word returned from the memory controller, and leave the lower 16 bits unconnected. Steve On Fri, 2004-10-01 at 00:03, <A HREF="http://www.opencores.org/mailman/listinfo/cores">verno at analogic-computers.com</A> wrote: [q] Dear Rudi, Just one question, please anwser it isn't difficult and no time need the designer of the memctrl. I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits? Thank you yours anwsers. Best regards: Erno Varga ----- Original Message ----- From: Rudolf Usselmann<<A HREF="http://www.opencores.org/mailman/listinfo/cores">rudi at a...</A>> To: Date: Wed Sep 29 13:32:30 CEST 2004 Subject: [oc] memctrl [q]> On Wed, 2004-09-29 at 17:11, <A HREF="http://www.opencores.org/mailman/listinfo/cores">verno at a...</A> wrote: [q] > Dear All, > > So nobady use this module? > > Erno [/q] > There are quite a few users of the Memory Controller including > numerous > commercial users ... > But I think everybody is busy and has no time to provide free > tech support ... > rudi > [/q] ====================================================== ======= [q]> Rudolf Usselmann, ASICS World Services, <A HREF="http://www.asics.ws">http://www.asics.ws</A> > Your Partner for IP Cores, Design, Verification and Synthesis > > [/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] -- Steven R. McQueen McQueen Technologies, Inc. (951) 809-3232 <A HREF="http://www.opencores.org/mailman/listinfo/cores">srmcqueen at mcqueentech.com</A> Erno: For single word reads, of course you can simply use the first 16 bits and ignore the rest of the bus. If you want to read bursts through a 16 bit bus, you will just need a 16 bit memory. In burst mode, the memory itself does the address increment, and the controller simply picks the data in sequence as it appears on the bus. Strictly speaking, you probably don't even need to change the memory controller, since it works on word addresses rather than byte addresses. Just write glue logic that reads the upper 16 bits of each word returned from the memory controller, and leave the lower 16 bits unconnected. Steve On Fri, 2004-10-01 at 00:03, verno at analogic-computers.com wrote: Dear Rudi, Just one question, please anwser it isn't difficult and no time need the designer of the memctrl. I use it in assincron mode with a flash, I can erase sector, write, and read. The flash has a 16 bits data bus, and the memory controler also 16 bits mode. When I read from the flash the controler put the address to the address wire and in the same chip enable cycle increment the address (because to assemble two 16bits to one 32 bits). When it happend my AMD memory on the upper 16bits give me full ones. My question is that could this device read two 16 bits in two individual chip enable cycle and after it could assemble to 32bits? Thank you yours anwsers. Best regards: Erno Varga ----- Original Message ----- From: Rudolf Usselmannrudi at a...> To: Date: Wed Sep 29 13:32:30 CEST 2004 Subject: [oc] memctrl > On Wed, 2004-09-29 at 17:11, verno at a... wrote: > Dear All, > > So nobady use this module? > > Erno > There are quite a few users of the Memory Controller including > numerous > commercial users ... > But I think everybody is busy and has no time to provide free > tech support ... > rudi > ====================================================== ======= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and Synthesis > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -- Steven R. McQueen McQueen Technologies, Inc. (951) 809-3232 srmcqueen at mcqueentech.com

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