hello
does anybody could hint on how to migrate wishbone based core into plb one?
(plb46 I mean).
it seems like plb2wb bridge on opencores already out of date according to wishbone standard (B3) and so 2 signals aren't present in it:
## Wishbone master B3 extended with 2 signals: "Cycle Type Identifier" and "Burst Type Extension"
m_wb_cti_o
m_wb_bte_o
.
thanks

just as a side note:

xilinx and altera are moving away from there currently used system-on-chip busses toward amba axi4.

if you are in early stages in your design it could be helpfull to think again about the bus system you use.
if you are on the way to extend a existing design then it's clear that you stick to plb46. xilinx will still support it some time (you should ask them for how long exactly).