Hi,

I downloaded the latest version of wb_conmax from OpenCores.

And then, I found that there are neither CTI nor BTE signal input in wb_conmax_top.v RTL code.

Doesn't wb_conmax support Wishbone's burst transfers?

If wb_conmax does not support burst transfer, is there some other Wishbone Interconnect Matrix IP supporting burst transfer?

Hi,

That's a fairly old arbiter. The ones in ORPSoC do support bursting, but they do not have their own project, nor are they automatically configured.

http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v

That's the one for the data bus. There's a define to control whether registering is used, but with registerting you don't get burst functionality at present. These all need to be updated for Wishbone B4 (adding pipelining, making registered bursting through the arbiter a whole lot easier).

I tried "arbiter_dbus.v", but I found that it have problem with access 2 masters to 1 slave simultaneously.

I've been working on an improved version that could replace arbiter_dbus and arbiter_ibus and will handle multiple masters. Not quite done yet, but I can send a message when I have something that passes the ORPSoC regression tests

2 olof
it would be great