In simple Asynchronous fifo , writing using clk1 & reading using clk2 , now i m trying to implement the Full & Empty Status flag for that i
==> Set the Direction Signal to High when Write_address( or Write_pointer ) is less than Read_address( or Read_pointer ) &&
i.e. ( Write_pointer > Read_pointer ) then Direction = 1;

Reset the Direction Signal to Low when Write_address( or Write_pointer ) is greater than Read_address( or Read_pointer )
i.e. ( Write_pointer
Case 1: ( Full Flag )
I assert status Full flag When Direction Signal is Set to High && ( Write_pointer == Read_pointer ).,
i.e. ( Direction == 1 && ( Write_pointer == Read_pointer ) ) then Full = 1;

if not i deassert status Full flag to Zero (Low).

Case 2: ( Empty Flag )
I assert status Empty flag When Direction Signal is Set to Low && ( Write_pointer == Read_pointer ).,
i.e. ( Direction == 0 && ( Write_pointer == Read_pointer ) ) then Empty = 1;

if not i deassert status Empty flag to Zero (Low).

Here I have Problem when Comparing Write_pointer && Read_pointer to assert Empty or Full
i.e. ( Write_pointer == Read_pointer )

because here the two Pointers are from Two differernt clk domains so i need to do double synchronization for anyone of the Pointer for synchronization with respect to the other clk domain .

During Comparision of Pointers now i can compare only Write_pointer with two clk delay Read_pointer because of Double synchronization of Read_pointer.
i.e. ( Write_pointer == two_clk_delay_Read_pointer )

if i compare like above equation means i am having the problem of missing the exact ( Write_pointer == Read_pointer ) condition ..........
but i want to compare the exact ( Write_pointer == Read_pointer ) .

So Plz givre me solutions regarding or if you are following any buffer mangement techniques kindly discuss.

thank you for your time.

Check out the sd_fifo_s component from sdlib; this is a reasonably standard implementation of an asynchronous FIFO.

The Advanced Debug System project has a working implementation of asynchronous FIFOs, there are two of them in the adbg_jsp_biu module. They're used to pass data between the JTAG clock domain and the WishBone clock domain.

Er,In my understanding about you problem. I think that you can compare the wirte_pointer and the read_pointer just logicly. Neither in the clk1 domain nor in the clk2 domain.