Hi,
Does any body knows where can I get an SPI core that has been written in VHDL?
Thanks,
Idan

Verilog isn't that difficult to read and understand, and SPI core is quite small. Suggest you translate a Verilog core to VHDL, if you cannot find a VHDL core. The translation will help you to understand the core and how it works, which is always a good idea when integrating a new core into your design.

For example xapp386: CoolRunner-II Serial Peripheral Interface Master
Last link is:
ftp://ftp.xilinx.com/pub/applications/refdes/xapp386.zip

You can find one here:
http://opencores.org/project,spi_master_slave
There are actually two cores in that project, one for a master interface and one for a slave interface.
Both are very small RTL descriptions, written in VHDL, and handle the parallel read/write interface like a synchronous RAM.
You can select the SPI mode and word size as generics.
The cores were developed as technology independent designs, but follow the coding style recommended by Xilinx for Spartan-6 and newer CLB capabilities, such as reduced control set usage and reduced RESET / PRESET usage.
So far, it synthesizes very well in Spartan-6, with 44 slices for a master+slave modules.

The spi cores above were used in several projects, and were optimized for operation at over 100MHz, using only CLB bulk logic. The project has testbenches and FPGA hardware verification data.

Jonny

Hello sir,
I am writing the vhdl code to interface microcontroller and spi. In my project I have to interface spi externally. But i have a doubt if we are connecting spi externally is there any need of memory. Because there are multiple slaves connected to the spi. Please help me.

Need of memory? Please elaborate.

- Jonny

hii to all,

how to interface ADC128s022 using SPI in VHDL, as well as i want to use 8 channels of ADC128s022. How can i make this using spi

http://opencores.org/project,spi_master_slave