Hello,

I am trying to interface with adjd-s371-q999 color sensor.
It is only one master and one slave in the design, so I am using simple I2C code of opencores.
Along with the I2C code there was an example of interface with ds1621 temperature sensor, I followed that example, made some changes, but it's not working - oscilloscope does not sense signals. Later I figure out that I should use pull up resistors, and I did so, but no use :( Here is my code, what I am doing wrong? Please help. [Altera board, cyclone II FPGA]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

use work.i2c.all;

entity adjd_s371_q999 is
port (
CLOCK_27 : in std_logic;
KEY: in std_logic_vector(2 downto 2);
SW: in std_logic_vector(5 downto 5);
LEDG: out std_logic_vector(7 downto 0); -- data read from ds1621

LEDR: out std_logic_vector(0 downto 0); -- no correct ack received
gpio_0: inout std_logic_vector(1 downto 0) -- scl and sda
);
end entity adjd_s371_q999;

architecture structural of adjd_s371_q999 is
-- Registers
constant DATA_RED_LO: std_logic_vector(7 downto 0) := x"40";
constant DATA_RED_HI: std_logic_vector(7 downto 0) := x"41";
constant DATA_GREEN_LO: std_logic_vector(7 downto 0) := x"42";
constant DATA_GREEN_HI: std_logic_vector(7 downto 0) := x"43";
constant DATA_BLUE_LO: std_logic_vector(7 downto 0) := x"44";
constant DATA_BLUE_HI: std_logic_vector(7 downto 0) := x"45";

constant SLAVE_ADDR : std_logic_vector(6 downto 0) := "1110100";

constant CLK_CNT : unsigned(7 downto 0) := conv_unsigned(20, 8);

signal clk : std_logic;
signal nReset : std_logic;

signal Dout : std_logic_vector(7 downto 0); -- data read from ds1621

signal error : std_logic; -- no correct ack received

signal cmd_ack : std_logic;
signal D : std_logic_vector(7 downto 0);
signal lack, store_dout : std_logic;

signal start, read, write, ack, stop : std_logic;
signal i2c_dout : std_logic_vector(7 downto 0);

begin
-- hookup I2C controller
u1: simple_i2c port map (clk => clk, ena => '1', clk_cnt => clk_cnt,
nReset => nReset, read => read, write => write, start => start,
stop => stop, ack_in => ack, cmd_ack => cmd_ack, Din => D,
Dout => i2c_dout, ack_out => lack, SCL => gpio_0(0), SDA => gpio_0(1));

clk nReset LEDG LEDR(0) gpio_0(2) init_statemachine : block
type states is (t1, t2, t3, t4, t5);
signal state : states := idle;
begin
nxt_state_decoder: process(clk, nReset, state)
variable nxt_state : states;
variable iD : std_logic_vector(7 downto 0);
variable ierr : std_logic;
variable istart, iread, iwrite, iack, istop : std_logic;
variable istore_dout : std_logic;
begin
nxt_state := state;
ierr := '0';
istore_dout := '0';

istart := start;
iread := read;
iwrite := write;
iack := ack;
istop := stop;
iD := D;

case (state) is

-- READ COLOR
-- 1. send start condition
-- 2. send slave address + write
-- 3. check ack
-- 4. send register address
-- 5. check ack
-- 6. send start condition
-- 7. send slave address + read
-- 8. check ack
-- 9. read read byte
-- 10. send not ack

when t1 => -- send start condition, sent slave address + write
if (cmd_ack = '1') then
nxt_state := t2;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no acknowledge received from last command, expected ACK
end if;

istart := '1';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := (slave_addr & '0'); -- write to slave (R/W = '0')
end if;

when t2 => -- send register address
if (cmd_ack = '1') then
nxt_state := t3;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no acknowledge received from last command, expected ACK
end if;

istart := '0';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := DATA_RED_LO;
end if;

when t3 => -- send (repeated) start condition, send slave address + read
if (cmd_ack = '1') then
nxt_state := t4;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no acknowledge received, expected ACK
end if;

istart := '1';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := (slave_addr & '1'); -- read from slave (R/W = '1')
end if;

when t4 => -- read MSB (hi-byte), send acknowledge
if (cmd_ack = '1') then
nxt_state := t5;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no acknowledge received from last command, expected ACK
end if;

istart := '0';
iread := '1';
iwrite := '0';
iack := '0'; --ACK
istop := '0';
end if;

when t5 => -- read LSB (lo-byte), send acknowledge, sent stop
if (cmd_ack = '1') then
nxt_state := t1;

istart := '0';
iread := '1';
iwrite := '0';
iack := '1'; --NACK
istop := '1';

istore_dout := '1';
end if;
end case;

-- genregs
if (nReset = '0') then
state error store_dout
start read write ack stop D '0');
elsif (clk'event and clk = '1') then
state error store_dout
start read write ack stop D end if;
end process nxt_state_decoder;
end block init_statemachine;

-- store temp
gen_dout : process(clk)
begin
if (clk'event and clk = '1') then
if (store_dout = '1') then
Dout end if;
end if;
end process gen_dout;

end architecture structural;

Having the same problem, does any one has a working example with I2C?

Are you using open-drain buffers?

2 kabzone
Can you point to exact Opencores name of "simple_i2c" module?