In uart_regs.v
// rf_pop signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
rf_pop else
if (rf_pop) // restore the signal to 0 after one clock cycle
rf_pop else
if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
rf_pop end

If 'wb_re_i' is too long refer to the clk, 'rf_pop' may active
more than once.Then the RX FIFO will pop more than one data but
the CPU only read one. For example, bus colock is 10MHz,UART core
clk is 50MHz,and suppose 'wb_re_i' hold one bus colock that is
100ns,but the UART core generate 'rf_pop' by 10ns,so 'rf_pop' will
active 5 times theoretically. This problem is found when I implement
the core in a EP2C8Q208, CPU only receive some of the data from RXD
line.
I change it to a form like the 'tf_push' genarting(following),
then the problem is solved.
// rf_pop signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
rf_pop else
if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
rf_pop else
rf_pop end