I m working with this TG68k core in Cyclone II using QuartusII. I have problems with pin planner. There is more pins than in standard 68 pin mc68k. Ok i understand most things, but what i can do with Data_in and Data_write. Is this Data Bus D0-D15 I/O on MC68k because if it is i dont know how to assign those pins, because i have 16 Data_in and the same number od Data_write, i cant combine them to get 16 Data Bus I/O pins and then to connect it to Mc68k. I need to use 32 pins and what to do with them i cant connect it to 16 pins of Data Bus.

Here is code i dont so far:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY data_bus IS
PORT(
data_bus : inout STD_LOGIC_VECTOR (15 downto 0);
oe : IN STD_LOGIC;
input : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
END data_bus;

ARCHITECTURE signals OF data_bus IS
signal data_in : STD_LOGIC_VECTOR (15 downto 0);
signal data_out : STD_LOGIC_VECTOR (15 downto 0);
signal data_oe : STD_LOGIC;

BEGIN
PROCESS(oe)
BEGIN
IF oe = '1' THEN
data_bus ELSE
data_bus data_in
END IF;
END PROCESS;
END signals;

hey majsta,

I don't know the TG68k core in Cyclone II , but I know how to build a bi-directional communication bus. I think, as far as I understood you right, it is what you wanted to do. This is quite easy, so my suggestion would be the following:
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity bus_switch is
generic(
D_BUS_WIDTH : integer := 8 -- data bus width (default 1 Byte)
);
port (
clk : in std_logic; -- if you would a clk sync communication
ena : in std_logic; -- data dir
i_data : in std_logic_vector(D_BUS_WIDTH-1 downto 0); -- input data
o_data : out std_logic_vector(D_BUS_WIDTH-1 downto 0); -- out data
b_data : inout std_logic_vector(D_BUS_WIDTH-1 downto 0) -- bi-directional communication bus
);
end bus_switch;

architecture arch of bus_switch is

signal s_i_data : std_logic_vector(D_BUS_WIDTH-1 downto 0); -- input data signal
signal s_o_data : std_logic_vector(D_BUS_WIDTH-1 downto 0); -- output data signal

begin
-----------------------------------------------------------------------------
-- Data bus access
-----------------------------------------------------------------------------

o_data s_i_data
-- purpose: to handle the access on the bi-directional bus
-- type : combinational
-- inputs : s_bus_trans_dir
-- outputs:
bus_access : process (clk, ena)

begin
if ena = '1' then
b_data else
b_data 'Z');
if rising_edge(clk) then
s_o_data end if;
end if;
end process bus_access;

end arch;

---------------------------------------------------------------

The HW description above is one example there are others as well as simplifications. I guess this example provides an easy as well as understandable way for getting the idea about bi-directional bus communication.

Cheers,
Andreas

Yes thank you i solved the code and it is working now, but still no connection to tg68 core. Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY data_bus IS
PORT(
data_bus : inout STD_LOGIC_VECTOR (15 downto 0);
oe,clk : IN STD_LOGIC;
inp : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
outp : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END data_bus;

ARCHITECTURE signals OF data_bus IS
signal data_in : STD_LOGIC_VECTOR (15 downto 0);
signal data_out : STD_LOGIC_VECTOR (15 downto 0);

BEGIN
PROCESS(clk)
BEGIN
IF clk = '1' AND clk'EVENT THEN -- Creates the flipflops
data_in outp END IF;
END PROCESS;

PROCESS(oe, data_bus, data_in)
BEGIN
IF oe = '1' THEN
data_bus data_out ELSE
data_bus data_out END IF;
END PROCESS;
END signals;