Hello FPGA/IC designers,

I've written an FPGA project structure specification that may be of interest,

https://www.boldport.com/docs/fpgaproj

I make the case for why structure is essential for effective IP integration, etc. I'm looking for feedback, good or bad. Feel free to email me directly at saar@boldport.com

While I'm at it, let me shamelessly promote my project that aims to make FPGA design better structured, transparent and easy:

http://www.boldport.com

I'm looking for early adopters, and feedback goes a long way at this stage; I'm happy to help any project migrate to the boldport flow.

Thanks, saar.

Hi,

I like the idea of standardizing FPGA project structure. Hardware design is often a mess. I have read your proposal, and most of it looks fine so far. I have a few concerns regarding naming however. Many opencores IP blocks have a naming scheme where the source code is placed under rtl/$(programming language) instead of sources/$(programming language), as you propose. Also, I'm not keen on the idea to have verilog and vhdl under a hdl directory in sources. That feels like an unnecessary extra directory level.

Same thing applies to simulation, which I would like to shorten to sim.

The rtl and sim names are even used by other tools, like coregen, so it would make sense to use these names for that reason too

//Olof

Hi Olof,

Thanks for your feedback!

Honestly, I'm not too concerned about names at this stage. In writing this document I went with my own preferences though that doesn't mean that those will prevail in the long run. Consistency is the only thing that matters, not the actual names. One could also envision a personal naming mapping file that will make sure to keep things in order. Naming is not the main problem to overcome.

Feel free to contact me directly at saar@boldport.com with further comments.