I've found myself confused with some of wishbone's transfer types. I'm working on a bridge between Wishbone and something else, and would like to support something that's similar to PCI's burst transfers, where large amounts of data can go on successive clocks. I think Wishbone calls such a thing pipelines transfers. But then there's block transfers, and I don't understand them well, and I keep wanting to call the wishbone translation of burst transfers to be block transfers.

What's the difference, and how to I keep then straight in my head better?

There are two types of burst transfer defined in the wishbone specification. Both
can transfer data on consecutive cycles.

By setting Cycle Type Identifier, CTI_O, to incrementing burst cycle (3'b010) you start a burst cycle.
Data can be transfered on every cycle. Each data transfer is acknowledge before next cycle can start.

Wishbone release B4 adds an alternative way of burst cycle. The reason is to better support wishbone
slaves or bridges with FIFO internally. During burst traffic a new cycle is started when cycle and
strobe is active. This is what we mean by pipelined traffic. The FIFO act like the pipeline and a
number of commands (bus cycles) can be in the pipeline. Each cycle is acknowledge upon completion.
A new signal, STALL, is introduced to limit the depth of pipelining. This signal acts a bit like
a FIFO full flag.

The later model is very well suited to wishbone bridge design where the wishbone bus is in one clock domain and the other bus (could be PCI) has its own clock domain. An async FIFO in the
bridge take care of pipelining and clock domain crossing

/Michael Unneback
ORSoC

OK, I think I had mistakenly tried to apply one or the other of those words (block or pipelined) to mean burst.