Hi! I've just started with FPGA, so bear with me. (I have more answers than questions today :)

I'm playing with my new IGLOO nano kit and Libero (which I'm learning to love), for it I did some simple things and then jumped to using "Nugroho Free Hash Cores" (http://opencores.org/project,nfhc,Overview)

It has implementations for SHA-1, SHA-256 and SHA-512. I've only used SHA-1

To plug it into my design I changed all bit and bit_vector for std_logic and std_logic_vector (first questions here: it simplified the code a lot (castings), but how does that affect the overall performance? (size, power, speed, etc).

Also, I've been simulating and drawing waves, and had a hard time figuring out if the SHA-1 implementation was correct or not (I do have "lots" of experience with crypto).

It turned out that the implementation (at least SHA-1) lacks the mandatory padding step, what could be a headache for people trying to use it. (other than that it works fine)

I guess your design is supposed to care about padding outside.

just that, a comment. No further questions, except that I'd like to collaborate this, documenting a little bit more the Project, but I don't know how. so, how? Should I also collaborate my changes (bit -> std_logic)?

uhm... will I receive answers on my email?

gera

PS: This core is BSD, that's why I chose it, the other I've checked (/project,sha_core) and although the C code (from src/) does handle the padding, I don't see it in rtl/. So I guess no-padding is expected?