hi i am working on i2c_master_salve_core, developed by Mr.Atish Jaiswal on vmm methodology.
I need a clarification on the scl and sda lines as it is splited into sda_o,sda_oe,sda_in and respectively for scl clock also.

another pieceof code added to
vmm_i2c_top.sv file

assign dut_sda_o = 1'b0;
assign temp_sda = pif.sda_oe & dut_sda_oe;
assign temp_scl = pif.scl_oe & dut_scl_oe;
assign pif.sda = temp_sda ? 1'bz : 1'b0;
assign pif.scl = temp_scl ? 1'bz : 1'b0;

how pif.sda_oe & pif.slc_oe works from the test bench point of view

can any one give explianation for this?
I need it is urgent.

I'm not quite sure which core you are talking about. Could you provide a link to the project?

Anyway, it seems like the _o, _oe and _in lines are supposed to be connected to an external tristate buffer to avoid having that in the core.

If _oe is 1, then you can read the output from the device, but not write to it. Otherwise, the device outputs z, and you can write to it's input

Hi,
this is the link for the block

http://opencores.org/project,i2c_master_slave_core

-Thanks
-Sravan