Hello all, I ahve a few qurey . I need to know how can i generate test pattern for a ckt say multipier implemeted on fpga. i need test the ckt for faults due to delay. thanking in advance bye ys --------------------------------- Do you Yahoo!? Yahoo! Photos - Get your photo on the big screen in Times Square -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20031224/ac8b3c06/attachment.htm

I have been thinking about a project where I would need an interface for a bunch digital I/O for a PC running Linux with some real-time extensions. I actually need a bit more then simple I/O but it is of no consequence. I was originally thinking of using a Memec Insight 2S200 PCI board but it occurred to me that I might possibly be able to use Ethernet. If I used the OC Ethernet core would I need to include some sort of [soft] processor (i.e. the OpenRISC processor) as a glue between the network interface and my I/O, quadrature decoders and associated logic?

Thanks for your time.

--adam

On Sat, 2004-01-10 at 17:24, Hunt, Adam wrote:
I'm thinking about something similar, a bunch of IOs for a PC running Linux. However I am thinking to use either Parallel Port or USB 1.1. With my USB 1.1 IP, I could do that with a single endpoint (control) and use Vendor IO as GPIO (16 address lines and 16 bit data). My main application is to control lighting and other features (alarm) in my house. I am also interested in building a low cost Logic Analyser (and may be even DSO) if I can find somebody to do the software portion. Problem is that USB 1.1 has a rather limiting bandwidth for that. My objective is also to be CPU free (at most may be a PIC). Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/

On Sat, Jan 10, 2004 at 06:28:01PM +0700, Rudolf Usselmann wrote:
I've run home controls for a few years. I'd strongly recommend lots of simple distributed boards (eg single pic level) and do all wiring as differential serial - ie RS485. interference to radios and ground bounce and lightning in the area are the issues. You want to be able to run over cheapo 4conductor round telephone wire. The system I'm running has a few PIC boards talking to a polling host (an HC11) all battery backed. The poll host talks to a PC serially. Upgrading the polling box with USB or ethernet would be a good project though. It runs code (currently forth) downloaded at powerup. The PC logs (eg temp, rainfall, door activity) and issues time based commands. I can publish this if there is any interest, but its hardly a core. for DSO/logic analyzer, have a look at the bitscope http://www.bitscope.com its along those lines. Since it (used to?) get by with async, usb1.1 should suffice. Perhaps a cleaner hardware implementation could run with lightly modified code? john

If you're looking into Home Automation I have a friend who's using x10 for that, and it work very well for him. It's a different approach as it's using the power line for communication. He has a good web site a bout it at http://www.geocities.com/ido_bartana/ Hope it helps some of you. Erez. ----- Original Message ----- From: "Hunt, Adam" ahunt at solvone.com> To: "OpenCores List (E-mail)" cores at opencores.org> Sent: Saturday, January 10, 2004 11:24 PM Subject: [oc] (no subject)
bunch digital I/O for a PC running Linux with some real-time extensions. I
actually need a bit more then simple I/O but it is of no consequence. I was
originally thinking of using a Memec Insight 2S200 PCI board but it occurred
to me that I might possibly be able to use Ethernet. If I used the OC
Ethernet core would I need to include some sort of [soft] processor (i.e.
the OpenRISC processor) as a glue between the network interface and my I/O,
quadrature decoders and associated logic?

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Hi, Is there any body used oc8051 core and synthesis into gate level netlist and simulation passed? I used artisan two block 32K word depth 16bit address input and 8 bit data output. I can simulation at RTL level passed all 122 items instructions, but when synthesis oc8051 all block (except memory)into gate level. I find rom read data and output has a middle data output. so oc8051 can not work correctly. Please any one give me some advise. Thanks! Junhu_Wang. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20040402/bcf59537/attachment.htm

 Hi Sir i need DMA Controller nd my guide has told me 2 design a DMA Controller wid a some added feature or sumthing thats missing in existin dma controllr So i need ur help in my project for designng block diagram , specifications & verilog code Nirmol -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060814/7406959a/attachment.htm

Uhh, isn't the point of this project and you education in general to learn how to do all of this yourself? If you're having issues coming up with the specs talk to your advisor. And do you honestly think someone's going to just do your whole project for you for free? Mike On 14 Aug 2006 07:18:48 -0000, engineers2gether engineers2gether at rediffmail.com> wrote: -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20060815/926012d6/attachment.htm

Mike Delaney wrote:

There is little doubt that certain pockets of the global community appear to foster, to a larger degree than the norm, belief that: (1) The whole point of education is to obtain qualifications that will allow one to start making money. Actually making the effort to understand the concepts being "taught" is a complete waste of time. (2) There's absolutely nothing wrong with asking (and expecting) someone else to do your work for you. There's no shame in taking complete working designs and passing them off as your masters thesis. I'm not sure whether it's getting worse, of the internet just makes it easier to get through. I recall sorting through a pile of assignments on telecommunications link power budgets and coming across a group of about 7 or 8 papers which were on *identical* excel spreadsheets with *identical* calculations, text labels, columns widths etc. Seems even making a token attempt to hide your plagiarism is too much effort! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266

Ongoing confusion regarding "free beer" and freedom I guess. Anyway the opencores FAQ is crystal clear on the topic: http://www.opencores.com/faq.cgi/section/2/2.6#2.6 Rich d ----- Original Message ----- From: Mark McDougallmarkm at v...> To: Date: Tue Aug 15 03:14:01 CEST 2006 Subject: [oc] (no subject)

Ongoing confusion regarding "free beer" and freedom I guess. Anyway the opencores FAQ is crystal clear on the topic: http://www.opencores.com/faq.cgi/section/2/2.6#2.6 Rich d ----- Original Message ----- From: Mark McDougallmarkm at v...> To: Date: Tue Aug 15 03:14:01 CEST 2006 Subject: [oc] (no subject)

Dear sir, please stop sending mails to my mail id Office firewalls, cyber cafes, college labs, don't allow you to download CHAT? Click here: http://in.messenger.yahoo.com/webmessengerpromo.php

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First off, I'm by no means a engineer. This message is going out to real
engineers that might have interest in bringing the idea I'm about to share
with you to reality. This idea came to me after some light reading about
rootkits on wikipedia and playing around with the program "rkhunter".

Malware designers are writing code that can infect a system via rootkits.
I've even read about the possibility of malware that can infect ROM chips on
mother boards as well as ROM chips on PCI cards. Meaning, anything that is
rewritable isn't safe from malware. Then it dawned on me that most of these
security issues could be minimized at the hardware level at preboot, meaning
before the operating system loads.

My brother brought his laptop to me complaning the internet wont work and that
it's slow as a whale turd. When I looked at it I found it swarming with
viruses. I asked him what happened to the firewall and antivirus that In
installed for him and he said he turned them off because the firewall was
messing with his internet and he didn't know how to turn it off with out also
turning off the antivirus. I think it was Eset Internet Security. I use
Linux on my system so I don't touch Windows software all that often. I've
come to the conclusion that it doesn't matter what software you put on there
or what you do, stupid users (and most users are stupid) will fsck up there
system.

That's when I decided that mother boards need to be dramatically redesigned
from the ground up with a proactive role in security. Now here's where I
will start with my wonderful idea that will save the world. You will either
see that world with me or you wont.

I'm sure most of you are aware of the history of the BIOS and the ROM's
they're on. Back in the day they really where ROM in every sense of the term
that they where READ only. They where embed on the board so you would need a
solder iron to remove them. Then they came out with the removable kind with
sockets that you can replace with a new chip. Then comes the kind you can
flash with software but are embedded. I'm sorry but impeded un-removeable ROM
chips are completely asinine. Now on to my idea.

Instead of one ROM chip for the BIOS there should be 3 and use "coreboot" as
the BIOS. All 3 will utilize sockets to be removeable for easy replacement.
The first chip will have the purpose as a backup of the default BIOS and the
chip will be read only. The second chip will house a copy of the primary
BIOS which will be rewritable and allow for updates. The third chip I will
call the ESP (Emergency Security Protocols) ROM which may or may not be read
only, I haven't decided yet. The third chip will have the open source
programs rkhunter, clamav and perhaps other programs that might be useful for
a preboot.

In the event the other two are corrupted for what ever reason you need only
flip a jumper, turn on the computer and the backup BIOS takes control and
allows you to wipe the other two chips and restore a rewritable copy of the
BIOS to chip 2 and the ESP BIOS to chip 3. The backup BIOS will also have
the Linux program "wipe" so in the unlikeliness a rootkit takes control of
chips 2 and 3 chip 1 will wipe it out and start from scratch.

This board will also have integrated wifi as well as lan making it easy to get
a internet connection. The goal being to be able to update the signatures of
rkhunter and clamav as well as update both firmware by direct download before
the OS even loads. This entire process will have a liberal use of checksums
to make sure at no time is any malware being installed during the preboot
process.

I'm still trying to work out the finer details in my head. So my idea may
make sense or it may not. Ultimately what I'm trying to do is build a mother
board with BIOS backup/security redundancy. The 3 chips act as a triad that
protect one another. The board should be designed so it tries to load the
second chip with the rewritable BIOS and use the third chip to do a quick
self scan for rootkits. If for some reason the first BIOS wont load it will
fall back on the backup BIOS restoring the primary. Perhaps some one can
share a better way of implimenting my idea. The goal is to make it damn near
impossible for malware to alter or change the BIOS or load at preboot. These
security meause could also be used to protect rewritable ROM on other
hardware.

Please share your thoughts. I would really like to see a board like this see
the light of reality.
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