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AES 128 bit simulation by s_gurmail on Aug 10, 2011			s_gurmail Posts: 1 Joined: Aug 20, 2010 Last seen: Aug 10, 2011
hello everybody. I am working on fully pipelined AES implementation using Xilinx 12.1.I sm using Hdl coding of Mr. Subhasis Das for the purpose. The results of synthesis and simulation are fine but the problem is the cipher text output is after a delay of 300ns.It is mentioned in test bench file also but when i try to make some changes in Op_start signal timings ,nothing positive occurs . Pls help regarding this . Can we make this latency delay smaller than this. Thanks in advance. hello everybody. I am working on fully pipelined AES implementation using Xilinx 12.1.I sm using Hdl coding of Mr. Subhasis Das for the purpose. The results of synthesis and simulation are fine but the problem is the cipher text output is after a delay of 300ns.It is mentioned in test bench file also but when i try to make some changes in Op_start signal timings ,nothing positive occurs . Pls help regarding this . Can we make this latency delay smaller than this. Thanks in advance.

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