Typically a verification environment would consist of 1. The RTL you are wanting to test...let's assume an AHB slave and the bus arbiter. 2. The BFM ( Bus Function Model ) which generates all the stimulus nessecary to test the RTL .... in our case the BFM would be an AHB master. 3. There would be a scoreboard which will check the data on the bus against the expected data ( expected data generation will depend on the functionality of the peripheral connected to your AHB slave ). 4. A protocol checker ... the monitor which will check whether all transactions have been conducted in accordance to the AHB protocol. This is typically done using assertions. 5. A functional/code coverage block. I would typically develop the monitor last when I have atleast a basic transfer going between my BFM and the RTL and the scoreboard is atleast partially functional. In anycase u need to explain a little more about your environment before anyone can help u or give u any suggestions. regards Unmesh -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20041019/0aaf935d/attachment.htm