Aurora 8B/10B IP error: Signals lane_up and channel_up from Aurora core become low occasionally during FPGA Virtex6 communication using SFP.
I tried to implement Serial Communication between FPGA XC6VL240T-1FF1156 on ML605 Board and xc6vlx240t-2ff1159 on HTG V6 PCIE Board using SFP. And aurora 8B/10B IP core was used as a high-speed serial solution. Example design projects derived from aurora IP core were synthesized and implemented to generated programming files (xx.bit).
However, signals lane_up and channel_up from Aurora 8B/10B IP core usually got low, which means lane initialization unsuccessful and aurora core cannot receive data.
I searched this error and found the root is Invalid Code from signal SOFT_ERROR in xxx_ERR_DETECT module ! �This usually means a bit was corrupted in transit, causing a good code to become unrecognizable.� I found this error description from table5-6: Error Signals in Simplex Cores in aurora_8b10b_ug353, but I have no idea how to deal with this issue.
I will appreciate you so much if you could give me some good advice.
Detailed description as attachment.
Thanks.

Does the signal into the transciever look good? You might need to check it with a high speed oscilloscope. Another test you can do is to directly instantiate the GTX primitive and use the built-in PRBS generator/detector.

Make sure also that you don't have buffer underflow/overflow. That might indicate that your clocks are in bad shape