Hi,

I am beginner in verilog. I was trying to write a code for bit stuffing .I am using siso(8 bits) The detection of 6 consecutive one is easy . But i didn't know how to insert a zero if 6 ones are detected.

Pls help me with the code

Thanks.
Shopi

Shopi,

One way is to use a bit shift FIFO to store the transmit bits and other parallel FIFO to keep track of where the bit stuffing occurs. When the bit stuff comes to the front you pause the data FIFO and send a stuff bit. For example:

assign allone = (txbits[5:0] == {6{1'b1}}) && (stuffbit[5:1] == 0);
assign txout = (txpause) ? 1'b0 : txbits[0];

always @(posedge clk)
begin
if (reset)
begin
txbits stuffbit txpause end
else if (txpause)
begin
stuffbit[0] txpause end
else
begin
stuffbit txbits txpause end // else: !if(txpause)
end // always @ (posedge clk)