Hello,

anyone know if exist a VHDL implementation of Z80SIO?
I'm plannin to port into FPGA an old control board based on
Z80 as CPU and Z80SIO as serial port controller.

What is this old computer you are trying to port over? I can maybe help.

I have some serial controller cores that I could wrap into a SIO interfacing circuitry. Can you offer a more detailed description of your project?
I love Z80, and would be nice to contribute.

Jonny

I started with the z80soc and created the z80control project. The project on the website uses the t80 and miniuart and comes with example code using the vector interrupts of the z80. I have since been working with this project but it is not in any stable version to upload to opencores yet. I have learn't alot since and am working on timing routines in vhdl for interfacing memory, interrupts, and I/O ports to the t80 core. It will have 4 port serial access and the memory is organized with locked ram, general purpose ram, with some page switching options all from z80 instruction. I am basically creating a custom microprocessor using the T80 core. Maybe we could collaborate by email and work on this together. It will in the end a least be a very customizable z80 microcontroller for who knows what application we may have in the future. My email is tylerapohl@gmail.com

The Z80A SIO (Z8440/1/2) is a very complex device. It has 2 complete full-duplex serial ports that can be configurable as full modem async UARTs, sync ports like IBM Bisync, HDLC/SDLC ports with auto bit stuffing/CRC, CRC-16/CCITT generation, X.25, and full Z80 interrupt and bus interfacing.
To have a full-compliant Z80SIO you must have a full-compliant Z80 cpu core that actually implements the exact Z80 pipeline and external signals, including the daisy-chain interrupt mechanism.

There is also the Z80 DART (Z8470), that is essentially the SIO with only async capabilities (dual UARTs). It has the same bus interfacing, but a programmable interrupt vector that also requires a compliant Z80 bus.

You can find the description of the SIO here: http://www.bitsavers.org/pdf/zilog/_dataBooks/Z80_DataBook.pdf

There is also the components databook: http://www.bitsavers.org/pdf/zilog/_dataBooks/1983_84_Components_Data_Book.pdf

So, to build a pure-blood Z80 system you will need to implement the full bus interfacing and datapaths.

The serial interfaces I use today do not implement the HDLC/SDLC/X.25/Bisync modes of the SIO, and I think a clean implementation would have to model the SIO from the ground up.

Jonny

That would be great to have a z80sio in vhdl. Have you seen the t80 project? It is the z80 core that would go perfect with the z80sio chip you plan on designing. I am very familiar with the z80sio chip but have not attempted to make it myself as the only features i need are interrupts and the ability to change baud rate. Are you planning to set this project in motion?

tylerapohl, you are asking from the op of this thread, ziotibia81?

I think this would be a nice project to contribute to, but the Z80SIO chip is a serious model in itself. Do you know if the t80 core implements all the details of the external bus signals, with the Z80 pipeline stages (T1, T2, TW, T3, T4) and all the interfacing modes?

Jonny

Yes the t80 fuctions just like the z80. The flaw with my current project is i did not properly handle the z80 bus timing t1,t2, etc. States. I am currently implementing these states and timing now. The routine will interface to memory and ports timed properly in the near future. I have experience in z80 cpu circuits as well as programming, so far the t80 works identical to the z80 spec from zilog. I am using a altera de1 board so my project uses the sram and flash chip on that board currently. The routine inputs the t80 pins and handles the timing to flash pins, sram pins and uart pins.

One way of doing this is to model the bus control signals, pipeline clock phases and interrupt control signals first, and make them work to access generic I/O registers. Then the serial core would be built for async and sync ports.
Other than the Z8340 SIO there is another, single-channel SIO, the Z80A SIO/9, that seems to have the same functionality as the Z8340 SIO, but is single channel. It appears that it was described in a 1978/1979 Zilog documentation. I have a brief description of its functions, and it seems to be a half Z8340 SIO chip.

I will monitor your progress with the t80 core, and will study the SIO specs a little bit to gain insight into a functional model. I may be able to contribute with a standard SIO core.

Jonny

Hi!!!
I'm planning to port into FPGA a TNC2 Clone. TNC2 is a Terminal Node Controller for AX25 packet radio. This controller is used by Ham Radio Operators.

On the net there are varius TNC2 versions but schematic is almost the same.

One version is there:

http://www.ir3ip.net/iw3grw/tnc2/tnc2s1.gif
http://www.ir3ip.net/iw3grw/tnc2/tnc2s2.gif

To make work a similar schematic a full complaint Z80 core and a Z80SIO with 2 serial port and HDLC is needed.

Others interesting project for Ham Radio world could be port into FPGA this:

http://www.ir3ip.net/iw3grw/sv/svhard.htm
http://www.symek.com/g/tnc3s.html

But I think that TNC2 is too simple...

I will be releasing a stable version of a project called z80control on opencores website within the next month. It uses a full complaint Z80 core and miniUart as the serial I/O. It would be use full to view this project in the next release and use it to modify miniUART to work like a complaint SIO core.

I think that could be easy to port into FPGA TNC2 schematic.

To try it over the air is nedded a modem like this:

http://ariagnochiampo.ir3ip.net/images/2400.jpg
or this:
http://www.amsat.org/amsat/articles/kd2bd/9k6modem/