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Problems accessing SDRAM with mem_ctrl
by Unknown on Oct 21, 2004 		Not available!
Hi folks,

I'm trying to access two 256Mb MT48LC16M16A2 Chips with the Memory
Controller, which I have hooked up with the RS232 System Controller for
testing purposes. Accessing the configuration registers works just fine,
no problems there. The chips are using CS0 and I've set the CSC0 to 0x91
to set the memory size to 256 Mb, bus width to 16 bit, type SDRAM and
enable this chip select. I've left everything else just as I've found
it. The registers now look like this:

60000000 : 00000000 00024A9A 000007FF 00000000
60000010 : 00000091 FFFFFFFF 00000000 00000000

So the SDRAM is initialized with some random noise - ok. Accessing the
chips gives me

00000000 : 00024A9A 00024A9A 00024A9A 00024A9A

Hmm... everything's the same... writing to it seems to work (writing
0xFF to address 0x0). Reading again

00000000 : 000000FF 000000FF 000000FF 000000FF

Hmpf... so now I'm stuck here. I've been following the manual to the
letter (I hope :)), wiring the memory controller to the wishbone and the
SDRAM. As I can access the configuration registers, the wishbone doesn't
seem to be the problem. The output to the chips is buffered, I've
checked the wiring of the pins at least twice... and I'm out of my depth.

I'd really appreciate some hints or help here...

Thanks in advance,
Alexander

P.S. If someone needs a bit of code or anything else, I'd be more than
happy to provide it in private email.

Problems accessing SDRAM with mem_ctrl
by Unknown on Oct 26, 2004 		Not available!
Sorry for being a pain in the a.., but could anyone *please* help me
with this? I really need to get the memory going!

Thanks again,
Alex

Alexander Wirtz wrote:
Hi folks, I'm trying to access two 256Mb MT48LC16M16A2 Chips with the Memory Controller, which I have hooked up with the RS232 System Controller for testing purposes. Accessing the configuration registers works just fine, no problems there. The chips are using CS0 and I've set the CSC0 to 0x91 to set the memory size to 256 Mb, bus width to 16 bit, type SDRAM and enable this chip select. I've left everything else just as I've found it. The registers now look like this: 60000000 : 00000000 00024A9A 000007FF 00000000 60000010 : 00000091 FFFFFFFF 00000000 00000000 So the SDRAM is initialized with some random noise - ok. Accessing the chips gives me 00000000 : 00024A9A 00024A9A 00024A9A 00024A9A Hmm... everything's the same... writing to it seems to work (writing 0xFF to address 0x0). Reading again 00000000 : 000000FF 000000FF 000000FF 000000FF Hmpf... so now I'm stuck here. I've been following the manual to the letter (I hope :)), wiring the memory controller to the wishbone and the SDRAM. As I can access the configuration registers, the wishbone doesn't seem to be the problem. The output to the chips is buffered, I've checked the wiring of the pins at least twice... and I'm out of my depth. I'd really appreciate some hints or help here... Thanks in advance, Alexander P.S. If someone needs a bit of code or anything else, I'd be more than happy to provide it in private email. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores



Problems accessing SDRAM with mem_ctrl
by Unknown on Oct 26, 2004 		Not available!
Surely a little bit of debugging information could be in order here.
For eample - what do the the SDRAM transactions on the pins look like?
Has the SDRAM been initialized (wait+precharge + couple refresh + mode
write ?

etc....

john


Alexander Wirtz wrote:

Sorry for being a pain in the a.., but could anyone *please* help me
with this? I really need to get the memory going!

Thanks again,
Alex

Alexander Wirtz wrote:

Hi folks, I'm trying to access two 256Mb MT48LC16M16A2 Chips with the Memory Controller, which I have hooked up with the RS232 System Controller for testing purposes. Accessing the configuration registers works just fine, no problems there. The chips are using CS0 and I've set the CSC0 to 0x91 to set the memory size to 256 Mb, bus width to 16 bit, type SDRAM and enable this chip select. I've left everything else just as I've found it. The registers now look like this: 60000000 : 00000000 00024A9A 000007FF 00000000 60000010 : 00000091 FFFFFFFF 00000000 00000000 So the SDRAM is initialized with some random noise - ok. Accessing the chips gives me 00000000 : 00024A9A 00024A9A 00024A9A 00024A9A Hmm... everything's the same... writing to it seems to work (writing 0xFF to address 0x0). Reading again 00000000 : 000000FF 000000FF 000000FF 000000FF Hmpf... so now I'm stuck here. I've been following the manual to the letter (I hope :)), wiring the memory controller to the wishbone and the SDRAM. As I can access the configuration registers, the wishbone doesn't seem to be the problem. The output to the chips is buffered, I've checked the wiring of the pins at least twice... and I'm out of my depth. I'd really appreciate some hints or help here... Thanks in advance, Alexander P.S. If someone needs a bit of code or anything else, I'd be more than happy to provide it in private email. _______________________________________________ http://www.opencores.org/mailman/listinfo/cores
_______________________________________________ http://www.opencores.org/mailman/listinfo/cores





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