1/1 
|
Atlys Spartan-6 Board
by kartik_ce on Sep 13, 2011 |
kartik_ce
Posts: 1 Joined: Sep 13, 2011 Last seen: Sep 13, 2011 |
||
|
Hello,
i m new to FPGAs. I have developed a sample project in which i am taking 2 input from BRAM, adding them and storing into another BRAM. I have simulate this design in Xilinx 12.4. it is working fine. Now i have sinthesize the design and i want to check it on Atlys Spartan-6 XC6SLX45 CSG324C board. can any one tell me how i can feed input clk and other signals to the board? or if there is any internal clock how can i use that? and how can i specify pin configurations in .CFG file? thanks in advance... |
|||
|
RE: Atlys Spartan-6 Board
by eteam on Sep 13, 2011 |
eteam
Posts: 32 Joined: Jun 5, 2009 Last seen: Mar 25, 2016 |
||
|
Check your post in the Xilinx user support forums.
This is a Xilinx design tools question. |
|||
|
RE: Atlys Spartan-6 Board
by jdoin on Sep 13, 2011 |
jdoin
Posts: 51 Joined: Sep 1, 2009 Last seen: Aug 27, 2026 |
||
|
how i can feed input clk and other signals to the board? or if there is any internal clock how can i use that? and how can i specify pin configurations in .CFG file?
The Atlys board has a onboard 100MHz oscillator, connected to a global clock buffer, that can be used directly. You have to use the .ucf file for the Atlys, that you can download from Digilent. |
|||
|
RE: Atlys Spartan-6 Board
by eng.sanchit on Oct 7, 2011 |
eng.sanchit
Posts: 10 Joined: Oct 6, 2011 Last seen: Nov 4, 2012 |
||
|
You don't necessarily need to download the .ucf file , only one constraint will be enough that is given in the documentation .
|
|||
1/1