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Internal output readout acknoledgement
by agentgates on Sep 19, 2011 |
agentgates
Posts: 2 Joined: Sep 17, 2011 Last seen: Feb 12, 2020 |
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Hi All,
I'm working with Verilog and trying to find a way how to reset a module after the data was read. Is there any standard way to do it? I mean is there anything like an internal flag in the module that returns with 1 after the module's outputs were read or shall I stay with the reset input? I'm just trying to minimise the interfaces to the module. Many thanks Kind Regards Tony |
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