OpenCores

OpenCores

XILINX easypath solutions

no use

no use

1/1

no use

no use

XILINX easypath solutions by unmesh on Oct 28, 2004			unmesh Posts: 13 Joined: Jan 5, 2004 Last seen: Feb 13, 2025
Hi All if wonder if anyone has any info on XILINX easypath solutions? have there been any design tape outs on easypath FPGAs. Thanks and regards Unmesh -------------- next part -------------- An HTML attachment was scrubbed... URL: <A HREF="http://www.opencores.org/forums.cgi/cores/attachments/20041028/85f95dc8/attachment.htm">http://www.opencores.org/forums.cgi/cores/attachments/20041028/85f95dc8/attachment.htm</A> Hi All if wonder if anyone has any info on XILINX easypath solutions? have there been any design tape outs on easypath FPGAs. Thanks and regards Unmesh -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20041028/85f95dc8/attachment.htm

XILINX easypath solutions by anon on Oct 28, 2004			anon Posts: 1 Joined: Nov 25, 2009 Last seen: Dec 21, 2009
I don't have experience of Xilinx easypath, but I do have one or two things to offer in response to your questions: Xilinx easypath is a service where Xilinx reduces its post-manufacture test set to only cover the device's suitability for a particular bitstream. So, when a product is ready to go to market, the customer provides Xilinx with their bitstream and it is used to confidently pass devices that would otherwise be failed. A trivial example: A design uses only 80% of the embedded multiplier units in a Virtex II part. As long as the multipliers made use of are operational who cares if the other multipliers are working? Note that if the bitstream changes (e.g. bug correction) there is no guarantee that it will work on easypath devices passed for the initial bitstream. It is interesting to note that over 90% of the programmability in the routing fabric is effectively "don't care" for any single design. Usually the device must be tested to ensure that all features are working before it can be shipped to the customer. I would bet Xilinx only offers Easypath on the larger devices. This is because manufacturing defects increase with the silicon area of the device. The smaller devices will have close to 100% yield and there is nothing to be gained from reducing the test set through easypath. ----- Original Message ----- From: unmesh<<A HREF="http://www.opencores.org/mailman/listinfo/cores">unmesh at s...</A>> To: Date: Thu Oct 28 06:52:46 CEST 2004 Subject: [oc] XILINX easypath solutions [q] Hi All if wonder if anyone has any info on XILINX easypath solutions? have there been any design tape outs on easypath FPGAs. Thanks and regards Unmesh -------------- next part -------------- An HTML attachment was scrubbed... URL: attachment.htm [/q] I don't have experience of Xilinx easypath, but I do have one or two things to offer in response to your questions: Xilinx easypath is a service where Xilinx reduces its post-manufacture test set to only cover the device's suitability for a particular bitstream. So, when a product is ready to go to market, the customer provides Xilinx with their bitstream and it is used to confidently pass devices that would otherwise be failed. A trivial example: A design uses only 80% of the embedded multiplier units in a Virtex II part. As long as the multipliers made use of are operational who cares if the other multipliers are working? Note that if the bitstream changes (e.g. bug correction) there is no guarantee that it will work on easypath devices passed for the initial bitstream. It is interesting to note that over 90% of the programmability in the routing fabric is effectively "don't care" for any single design. Usually the device must be tested to ensure that all features are working before it can be shipped to the customer. I would bet Xilinx only offers Easypath on the larger devices. This is because manufacturing defects increase with the silicon area of the device. The smaller devices will have close to 100% yield and there is nothing to be gained from reducing the test set through easypath. ----- Original Message ----- From: unmeshunmesh at s...> To: Date: Thu Oct 28 06:52:46 CEST 2004 Subject: [oc] XILINX easypath solutions Hi All if wonder if anyone has any info on XILINX easypath solutions? have there been any design tape outs on easypath FPGAs. Thanks and regards Unmesh -------------- next part -------------- An HTML attachment was scrubbed... URL: attachment.htm

XILINX easypath solutions by unmesh on Nov 2, 2004			unmesh Posts: 13 Joined: Jan 5, 2004 Last seen: Feb 13, 2025
where I think XILINX saves money is that it needs to only do a functional test of the design with test vectors provided by the designer... so that board testing time which runs out to quite a lot if the complete fpga chip is to be tested. i think its a rather smart way to sell defective dies... one question..does anyone know of any tapeouts on easypath...just curious.. thanks and regards Unmesh ----- Original Message ----- From: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">anon at anon.com</A>> To: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Sent: Thursday, October 28, 2004 9:20 PM Subject: Re: [oc] XILINX easypath solutions [q] I don't have experience of Xilinx easypath, but I do have one or two things to offer in response to your questions: Xilinx easypath is a service where Xilinx reduces its post-manufacture test set to only cover the device's suitability for a particular bitstream. So, when a product is ready to go to market, the customer provides Xilinx with their bitstream and it is used to confidently pass devices that would otherwise be failed. A trivial example: A design uses only 80% of the embedded multiplier units in a Virtex II part. As long as the multipliers made use of are operational who cares if the other multipliers are working? Note that if the bitstream changes (e.g. bug correction) there is no guarantee that it will work on easypath devices passed for the initial bitstream. It is interesting to note that over 90% of the programmability in the routing fabric is effectively "don't care" for any single design. Usually the device must be tested to ensure that all features are working before it can be shipped to the customer. I would bet Xilinx only offers Easypath on the larger devices. This is because manufacturing defects increase with the silicon area of the device. The smaller devices will have close to 100% yield and there is nothing to be gained from reducing the test set through easypath. ----- Original Message ----- From: unmesh<<A HREF="http://www.opencores.org/mailman/listinfo/cores">unmesh at s...</A>> To: Date: Thu Oct 28 06:52:46 CEST 2004 Subject: [oc] XILINX easypath solutions [q]> Hi All > if wonder if anyone has any info on XILINX easypath solutions? > have there been any design tape outs on easypath FPGAs. > Thanks and regards > Unmesh > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: attachment.htm > >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] Scanned by the SecureSynergy VirusScreen Service. For more information log on to : <A HREF="http://www.securesynergyonline.com">http://www.securesynergyonline.com</A> or <A HREF="http://www.securesynergy.com">http://www.securesynergy.com</A> where I think XILINX saves money is that it needs to only do a functional test of the design with test vectors provided by the designer... so that board testing time which runs out to quite a lot if the complete fpga chip is to be tested. i think its a rather smart way to sell defective dies... one question..does anyone know of any tapeouts on easypath...just curious.. thanks and regards Unmesh ----- Original Message ----- From: anon at anon.com> To: cores at opencores.org> Sent: Thursday, October 28, 2004 9:20 PM Subject: Re: [oc] XILINX easypath solutions I don't have experience of Xilinx easypath, but I do have one or two things to offer in response to your questions: Xilinx easypath is a service where Xilinx reduces its post-manufacture test set to only cover the device's suitability for a particular bitstream. So, when a product is ready to go to market, the customer provides Xilinx with their bitstream and it is used to confidently pass devices that would otherwise be failed. A trivial example: A design uses only 80% of the embedded multiplier units in a Virtex II part. As long as the multipliers made use of are operational who cares if the other multipliers are working? Note that if the bitstream changes (e.g. bug correction) there is no guarantee that it will work on easypath devices passed for the initial bitstream. It is interesting to note that over 90% of the programmability in the routing fabric is effectively "don't care" for any single design. Usually the device must be tested to ensure that all features are working before it can be shipped to the customer. I would bet Xilinx only offers Easypath on the larger devices. This is because manufacturing defects increase with the silicon area of the device. The smaller devices will have close to 100% yield and there is nothing to be gained from reducing the test set through easypath. ----- Original Message ----- From: unmeshunmesh at s...> To: Date: Thu Oct 28 06:52:46 CEST 2004 Subject: [oc] XILINX easypath solutions > Hi All > if wonder if anyone has any info on XILINX easypath solutions? > have there been any design tape outs on easypath FPGAs. > Thanks and regards > Unmesh > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: attachment.htm > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores Scanned by the SecureSynergy VirusScreen Service. For more information log on to : http://www.securesynergyonline.com or http://www.securesynergy.com

XILINX easypath solutions by RT on Nov 2, 2004			RT Posts: 10 Joined: Sep 2, 2009 Last seen: Sep 27, 2011
unmesh wrote: [q] where I think XILINX saves money is that it needs to only do a functional test of the design with test vectors provided by the designer... so that board testing time which runs out to quite a lot if the complete fpga chip is to be tested. i think its a rather smart way to sell defective dies... one question..does anyone know of any tapeouts on easypath...just curious..[/q] I don't know anything about Easypath, but I can't see that designers would provide "test vectors". Most FPGA designers do limited verification and couldn't produce the test vectors that would find problems in the FPGA fabric. What's much more likely, as 'anon' says, is that you provide a bitstream and Xilinx checks if it attempts to enable a faulty part of the device. Xilinx saves money because it can recycle faulty parts; it's nothing to do with reduced testing. You can't "tape out" on an FPGA; you just program it. I'd be surprised if Xilinx had many customers for this. The killer is that people buy FPGAs because they can reprogram them, and you probably can't reprogram an Easypath part. On the other hand, there is a (small) market for one-shot FPGAs, so maybe they'll sell some parts. I remember this used to be fairly common with DRAMs about 10 years ago - you could buy cheap faulty parts, and the part number told you which half of the device worked. The market went as yields went up. thanks and regards [q] Unmesh ----- Original Message ----- From: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">anon at anon.com</A>> To: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A>> Sent: Thursday, October 28, 2004 9:20 PM Subject: Re: [oc] XILINX easypath solutions [q]I don't have experience of Xilinx easypath, but I do have one or two things to offer in response to your questions: Xilinx easypath is a service where Xilinx reduces its post-manufacture test set to only cover the device's suitability for a particular bitstream. So, when a product is ready to go to market, the customer provides Xilinx with their bitstream and it is used to confidently pass devices that would otherwise be failed. A trivial example: A design uses only 80% of the embedded multiplier units in a Virtex II part. As long as the multipliers made use of are operational who cares if the other multipliers are working? Note that if the bitstream changes (e.g. bug correction) there is no guarantee that it will work on easypath devices passed for the initial bitstream. It is interesting to note that over 90% of the programmability in the routing fabric is effectively "don't care" for any single design. Usually the device must be tested to ensure that all features are working before it can be shipped to the customer. I would bet Xilinx only offers Easypath on the larger devices. This is because manufacturing defects increase with the silicon area of the device. The smaller devices will have close to 100% yield and there is nothing to be gained from reducing the test set through easypath. ----- Original Message ----- From: unmesh<<A HREF="http://www.opencores.org/mailman/listinfo/cores">unmesh at s...</A>> To: Date: Thu Oct 28 06:52:46 CEST 2004 Subject: [oc] XILINX easypath solutions [q]Hi All if wonder if anyone has any info on XILINX easypath solutions? have there been any design tape outs on easypath FPGAs. Thanks and regards Unmesh[/q] unmesh wrote: where I think XILINX saves money is that it needs to only do a functional test of the design with test vectors provided by the designer... so that board testing time which runs out to quite a lot if the complete fpga chip is to be tested. i think its a rather smart way to sell defective dies... one question..does anyone know of any tapeouts on easypath...just curious.. I don't know anything about Easypath, but I can't see that designers would provide "test vectors". Most FPGA designers do limited verification and couldn't produce the test vectors that would find problems in the FPGA fabric. What's much more likely, as 'anon' says, is that you provide a bitstream and Xilinx checks if it attempts to enable a faulty part of the device. Xilinx saves money because it can recycle faulty parts; it's nothing to do with reduced testing. You can't "tape out" on an FPGA; you just program it. I'd be surprised if Xilinx had many customers for this. The killer is that people buy FPGAs because they can reprogram them, and you probably can't reprogram an Easypath part. On the other hand, there is a (small) market for one-shot FPGAs, so maybe they'll sell some parts. I remember this used to be fairly common with DRAMs about 10 years ago - you could buy cheap faulty parts, and the part number told you which half of the device worked. The market went as yields went up. thanks and regards Unmesh ----- Original Message ----- From: anon at anon.com> To: cores at opencores.org> Sent: Thursday, October 28, 2004 9:20 PM Subject: Re: [oc] XILINX easypath solutions I don't have experience of Xilinx easypath, but I do have one or two things to offer in response to your questions: Xilinx easypath is a service where Xilinx reduces its post-manufacture test set to only cover the device's suitability for a particular bitstream. So, when a product is ready to go to market, the customer provides Xilinx with their bitstream and it is used to confidently pass devices that would otherwise be failed. A trivial example: A design uses only 80% of the embedded multiplier units in a Virtex II part. As long as the multipliers made use of are operational who cares if the other multipliers are working? Note that if the bitstream changes (e.g. bug correction) there is no guarantee that it will work on easypath devices passed for the initial bitstream. It is interesting to note that over 90% of the programmability in the routing fabric is effectively "don't care" for any single design. Usually the device must be tested to ensure that all features are working before it can be shipped to the customer. I would bet Xilinx only offers Easypath on the larger devices. This is because manufacturing defects increase with the silicon area of the device. The smaller devices will have close to 100% yield and there is nothing to be gained from reducing the test set through easypath. ----- Original Message ----- From: unmeshunmesh at s...> To: Date: Thu Oct 28 06:52:46 CEST 2004 Subject: [oc] XILINX easypath solutions Hi All if wonder if anyone has any info on XILINX easypath solutions? have there been any design tape outs on easypath FPGAs. Thanks and regards Unmesh

XILINX easypath solutions by Unknown on Nov 10, 2004			Not available!
[q]From my conversations with Xilinx reps, you're not buying defective dies. [/q] They throw a boat of wafers at the tester and run your program against them. The yields will be higher for your program because it only tests the part of the chip you use. Most designs only use a fraction of the routing resources available to the chip. I've heard numbers as low as single percentage points for typical designs. To not test these resources saves a lot of test time on an expensive tester. Less test time and higher yields = a cheaper product. There's no "tapeout" to speak of because it's still an FPGA and that FPGA is still loaded from your PROM. However, you can NEVER change your design because even the slightest change may not work. In that sense, you're locked into the design just as if you had an ASIC. However, you're paying a fraction of the NRE. There are several competing options. Altera HardCopy and several ASIC vendors are making streamlined Platform ASIC solutions. Each of these has its own set of benefits and hazards. Good luck. jason. ----- Original Message ----- From: unmesh<<A HREF="http://www.opencores.org/mailman/listinfo/cores">unmesh at s...</A>> To: Date: Tue Nov 2 05:25:28 CET 2004 Subject: [oc] XILINX easypath solutions [q] where I think XILINX saves money is that it needs to only do a functional test of the design with test vectors provided by the designer... so that board testing time which runs out to quite a lot if the complete fpga chip is to be tested. i think its a rather smart way to sell defective dies... one question..does anyone know of any tapeouts on easypath...just curious.. thanks and regards Unmesh ----- Original Message ----- From: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">anon at a...</A>> To: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A>> Sent: Thursday, October 28, 2004 9:20 PM Subject: Re: [oc] XILINX easypath solutions [q]> I don't have experience of Xilinx easypath, but I do have one [/q] or two [q]> things to offer in response to your questions: > > Xilinx easypath is a service where Xilinx reduces its [/q] post-manufacture [q]> test set to only cover the device's suitability for a [/q] particular [q]> bitstream. So, when a product is ready to go to market, the [/q] customer [q]> provides Xilinx with their bitstream and it is used to [/q] confidently [q]> pass devices that would otherwise be failed. > > A trivial example: A design uses only 80% of the embedded [/q] multiplier [q]> units in a Virtex II part. As long as the multipliers made use [/q] of are [q]> operational who cares if the other multipliers are working? [/q] Note that [q]> if the bitstream changes (e.g. bug correction) there is no [/q] guarantee [q]> that it will work on easypath devices passed for the initial [/q] bitstream. [q]> > It is interesting to note that over 90% of the programmability [/q] in the [q]> routing fabric is effectively "don't care" for any [/q] single design. [q]> Usually the device must be tested to ensure that all features [/q] are [q]> working before it can be shipped to the customer. > > I would bet Xilinx only offers Easypath on the larger devices. [/q] This is [q]> because manufacturing defects increase with the silicon area [/q] of the [q]> device. The smaller devices will have close to 100% yield and [/q] there is [q]> nothing to be gained from reducing the test set through [/q] easypath. [q]> > ----- Original Message ----- > From: unmesh<<A HREF="http://www.opencores.org/mailman/listinfo/cores">unmesh at s...</A>> > To: > Date: Thu Oct 28 06:52:46 CEST 2004 > Subject: [oc] XILINX easypath solutions > [q] > Hi All > if wonder if anyone has any info on XILINX easypath [/q] solutions? [q] > have there been any design tape outs on easypath FPGAs. > Thanks and regards > Unmesh > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: attachment.htm > > [/q] > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] Scanned by the SecureSynergy VirusScreen Service. For more information log on to : <A HREF="http://www.securesynergyonline.com">http://www.securesynergyonline.com</A> or <A HREF="http://www.securesynergy.com">http://www.securesynergy.com</A> [/q] From my conversations with Xilinx reps, you're not buying defective dies. They throw a boat of wafers at the tester and run your program against them. The yields will be higher for your program because it only tests the part of the chip you use. Most designs only use a fraction of the routing resources available to the chip. I've heard numbers as low as single percentage points for typical designs. To not test these resources saves a lot of test time on an expensive tester. Less test time and higher yields = a cheaper product. There's no "tapeout" to speak of because it's still an FPGA and that FPGA is still loaded from your PROM. However, you can NEVER change your design because even the slightest change may not work. In that sense, you're locked into the design just as if you had an ASIC. However, you're paying a fraction of the NRE. There are several competing options. Altera HardCopy and several ASIC vendors are making streamlined Platform ASIC solutions. Each of these has its own set of benefits and hazards. Good luck. jason. ----- Original Message ----- From: unmeshunmesh at s...> To: Date: Tue Nov 2 05:25:28 CET 2004 Subject: [oc] XILINX easypath solutions where I think XILINX saves money is that it needs to only do a functional test of the design with test vectors provided by the designer... so that board testing time which runs out to quite a lot if the complete fpga chip is to be tested. i think its a rather smart way to sell defective dies... one question..does anyone know of any tapeouts on easypath...just curious.. thanks and regards Unmesh ----- Original Message ----- From: anon at a...> To: cores at o...> Sent: Thursday, October 28, 2004 9:20 PM Subject: Re: [oc] XILINX easypath solutions > I don't have experience of Xilinx easypath, but I do have one or two > things to offer in response to your questions: > > Xilinx easypath is a service where Xilinx reduces its post-manufacture > test set to only cover the device's suitability for a particular > bitstream. So, when a product is ready to go to market, the customer > provides Xilinx with their bitstream and it is used to confidently > pass devices that would otherwise be failed. > > A trivial example: A design uses only 80% of the embedded multiplier > units in a Virtex II part. As long as the multipliers made use of are > operational who cares if the other multipliers are working? Note that > if the bitstream changes (e.g. bug correction) there is no guarantee > that it will work on easypath devices passed for the initial bitstream. > > It is interesting to note that over 90% of the programmability in the > routing fabric is effectively "don't care" for any single design. > Usually the device must be tested to ensure that all features are > working before it can be shipped to the customer. > > I would bet Xilinx only offers Easypath on the larger devices. This is > because manufacturing defects increase with the silicon area of the > device. The smaller devices will have close to 100% yield and there is > nothing to be gained from reducing the test set through easypath. > > ----- Original Message ----- > From: unmeshunmesh at s...> > To: > Date: Thu Oct 28 06:52:46 CEST 2004 > Subject: [oc] XILINX easypath solutions > > Hi All > if wonder if anyone has any info on XILINX easypath solutions? > have there been any design tape outs on easypath FPGAs. > Thanks and regards > Unmesh > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: attachment.htm > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores Scanned by the SecureSynergy VirusScreen Service. For more information log on to : http://www.securesynergyonline.com or http://www.securesynergy.com

no use

no use

1/1

no use

no use

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.