I have a question regarding the Ethernet IP Core Design Document written by Mr. Igor Mohor.

In section 2.3.7.2 "Tx and Rx Buffer Descriptors", the author gives an example of address
location calculations for both Tx and Rx core descriptor registers. According to what it
states earlier, the descriptor registers are located between address 0x400 to 0x7FF.

However, in the example, according to the calculation, the last Rx descriptor's location
is address: 0x7FC. As each descriptor register accommodates 8 addresses, it results that
its last address will exceed location 0x7FF - which contradicts the spec stated earlier.

Can someone clarify this point for me?

Thank you,

Abe

This is because the registers are 32-bit only. All the buffer descriptors consist of two 32-bit registers; one for control (including length and flags), and one for data pointer. An address ending in f is not 32-bit aligned, so the last register present is at 7fc, covering byte addresses 7fc-7ff. The last buffer descriptor, however, has an address of 7f8 since it is two registers. So the formulae calculate valid addresses to access (only 32-bit access is allowed) rather than address space covered or BD addresses.

I understand now.

Thank you for your answer.

Abe