Nowadays, In my application, I try to "REG8(I2C_BASE+I2C_CTR) = I2C_CTR_EN;"

after that , I do "uart_print_short(REG8(I2C_BASE+I2C_CTR));" (CTR's access is RW)

I found the result is 0x0.

Is it showing that I have problem in connecting I2C core to my system??

Thank you very much.

For correct answer on question "What's wrong?" its is not enough info.
For example, what exactly core do you use? Do you have sim environment in simulator?
If you have sim environment - what you can see at I2C master core input WB bus after: "REG8(I2C_BASE+I2C_CTR) = I2C_CTR_EN;" ? (etc)

sorry, I am green hand in the opencores, I use the core named " I2C controller core ".

How can I see at I2C master core input WB bus after: "REG8(I2C_BASE+I2C_CTR) = I2C_CTR_EN;" ?
I have no idea about that. So that I just read back the value of the register, found the result
is 0x0 which I supposed that I2C_CTR_EN didn't write into the register.

If you are talking about I2C-Master Core written by Richard Herveille, then you have IP core with Wishbone bus. So, you embedded it to your system. Plus, you also have CPU in your system (and some UART IF too, for print messages).

If you adopt it for Altera Avalon or Xilinx AXI, PLB -> usually FPGA vendors (Altera, Xilinx, etc) provides simulation environment in SoPC generation tool (in most cases it is just couple of clicks). And in the end of system generation, you will have simulation environment for Modelsim (or other simulator). In RTL simulation you can check every point of your design.
So, global steps in this case: 1) check HDL design (maybe you will find some mistakes and fix design at this step ;), 2) Create sim env for your system 3) Create TB (+some checkers, + waveforms, ...) 4) Run simulation and look what you have at input WB CFG port of I2C-Master Core (in accordance to your CPU C-code).

If you use pure WB interface + WB cross + own CPU (with WB IF) -> you must create all sim env "by hands".

Also, maybe you have problem with you C-code and/or UART module and/or C-compiler.
Because I have no full info about you setup, I can't give you more detailed help.

What bus width do you have, and what's the value of I2C_CTR? The I2C controller has 8-bit registers, but if you connect it to a 32-bit bus, all registers are 4 bytes apart...

Thank u kuzmi4 and bentwy.

Here I will list all my work to connect the core named "I2C controller core " written by Herveille, Richard to MinSoC.

The core's address is [2:0] 3 bits, data width is [7:0] 8bits

After adding the core.

I programmed as below

REG8(I2C_BASE + I2C_PRESC_HI) = 0x00;
REG8(I2C_BASE + I2C_PRESC_LO) = 49; //according to specification, this register is RW
REG8(I2C_BASE + I2C_CTR) = I2C_CTR_EN;
uart_print_short(REG8(I2C_BASE + I2C_PRESC_LO));

0x0 is printed on the minicom.

I think 0x2D (45) should be printed, right?
The method connecting core is same with uart core. (uart core is tested successfully)

Thank you!

Hi
I have a problem with the core.
I´m relativly new in VHDL (1,5 months)
I use Xilinx 13.1

scl & sda dosn´t toggle. In the past i archieved that a byte was send.
now the core makes only a start contidion.

I tryed to fix my fault. I need realy your help.
Thank you.

Hi
I have a problem with the core.
I´m relativly new in VHDL (1,5 months)
I use Xilinx 13.1

the core is
$Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $
-- $Date: 2009-01-20 10:38:45 $
-- $Revision: 1.8 $
-- $Author: rherveille $

scl & sda dosn´t toggle. In the past i archieved that a byte was send.
now the core makes only a start contidion.

I tryed to fix my fault. I need realy your help.
Thank you.