Aloha! While browsing the code for the common RTL models in the CVS I found a small nitpick in the generic_dpram dual port memory model. the generic_dpram contains independent resets for the read and write port (rrst and wrst). But these are only used when the memory instanciated is defined as VENDOR_XILINX. It's quite clear that some other vendors don't have resets for their memories, but, IMHO, if a reset port is present, at least the generic model (i.e. the actual model, not a vendor instanciated memory) should use the resets. For starters they could be codified to behave like the Xilinx memory. Should I add code for it? -- Med vänlig hälsning, Yours Joachim Strömbergson - Alltid i harmonisk svängning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÖTEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson at informasic.com Home: www.informasic.com ----------------------------------------------------------------------