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I2C master core's register
by Torsten2000 on Nov 4, 2011 |
Torsten2000
Posts: 5 Joined: Sep 26, 2011 Last seen: Dec 1, 2011 |
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Hello,
i habe a problem with the I2C master Core. In the past I archieved, that the core runned, but now I can´t do that. I use the Core: -- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $ -- -- $Date: 2009-01-20 10:38:45 $ -- $Revision: 1.8 $ -- $Author: rherveille $ an i have written a Testbench. I use Xilinx 13.1 O.40d I´m sorry for a silly question. I´m relativly new in VHDL (1,5 months) you can find the testbench (and the I2C Core) in the attachement. I hope you can help me. I tryed to find the fault but I don´t find.
Wave.jpg (280 kb)
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RE: I2C master core's register
by Torsten2000 on Nov 4, 2011 |
Torsten2000
Posts: 5 Joined: Sep 26, 2011 Last seen: Dec 1, 2011 |
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Here are the test bench
TESTBENCH_WB_I2C_M.vhd (6 kb)
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RE: I2C master core's register
by olof on Nov 4, 2011 |
olof
Posts: 218 Joined: Feb 10, 2010 Last seen: Dec 17, 2018 |
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You haven't connected the scl and sda pins to anything
scl_pad_o => open,
sda_pad_o => open,
SCL <= '0' when (scl_padoen_o = '0') else 'Z';
SDA <= '0' when (sda_padoen_o = '0') else 'Z'; Try changing this to:
scl_pad_o => scl_pad_o,
sda_pad_o => sda_pad_o, and
SCL <= scl_pad_o when (scl_padoen_o = '0') else 'Z';
SDA <= sda_pad_o when (sda_padoen_o = '0') else 'Z'; |
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RE: I2C master core's register
by Torsten2000 on Nov 4, 2011 |
Torsten2000
Posts: 5 Joined: Sep 26, 2011 Last seen: Dec 1, 2011 |
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Hello
thank you originally i have it like you have written. but this is not the fault, because scl_pad_o & sda_pad_o is always '0'. It must be another fault... :-| |
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RE: I2C master core's register
by olof on Nov 4, 2011 |
olof
Posts: 218 Joined: Feb 10, 2010 Last seen: Dec 17, 2018 |
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I just found the weirdest thing. There are comments on sda_pad_o and scl_pad_o in i2c_master_top.v
output scl_pad_o; // SCL-line output (always 1'b0)
output sda_pad_o; // SDA-line output (always 1'b0) and after tracking them down to i2c_master_bit_ctrl.v I can confirm that they are always set to 0
// assign scl and sda output (always gnd)
assign scl_o = 1'b0; assign sda_o = 1'b0; I have no idea what the reason for that is. Hopefully someone else can explain this |
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RE: I2C master core's register
by filepang on Nov 6, 2011 |
filepang
Posts: 23 Joined: Jul 2, 2009 Last seen: May 6, 2016 |
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Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a pull-up resistor.
when output pad of SCL, SDA disabled, external pull-up resistor raise this signal to logical high. |
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RE: I2C master core's register
by pcbeng25 on Nov 7, 2011 |
pcbeng25
Posts: 2 Joined: May 17, 2011 Last seen: Nov 11, 2013 |
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Yes, you have to have a pullup resistor on these lines for them to toggle. What this core does is control an enable of the sda and scl lines. When enable = '0', the lines are '0', and when the enable goes high, the scl and sda lines float and the pullup resistor pulls it to '1'. This is how I2C works. it is a bidirectional, open drain standard that requires a pullup. You will need to assign the scl and sda lines to 'H' in the test bench, and then you should see the functionality.
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RE: I2C master core's register
by hmcx18 on Nov 16, 2011 |
hmcx18
Posts: 10 Joined: Sep 10, 2011 Last seen: Dec 5, 2012 |
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Sorry, I have been out for one week.
I also have a problem in the rigister problem. and I solved it. My reason> because only 32-bit can connected to wishbone interface directly. I2C core is 8-bit. solution> you need a brige convert 8-bit to 32-bit which you can find in pacage of Minsoc. It works in my project. |
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