OpenCores

OpenCores

Can I get the time integrating correlator's verilog source code?

no use

no use

1/1

no use

no use

Can I get the time integrating correlator's verilog source code? by Unknown on Dec 24, 2003			Not available!
----- Original Message ----- From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">mysticdude117 at y...</A> To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> Date: Wed, 5 Nov 2003 15:40:41 +0100 Subject: Re: [oc] Can I get the time integrating correlator's verilog source code? [q] ----- Original Message ----- From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">sharma.amar at i...</A> To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">uzunlarovunc at h...</A> , <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> Date: Fri, 12 Sep 2003 10:18:54 +0200 Subject: Re: [oc] Can I get the time integrating correlator's verilog source code? [q]> > > > > ----- Original Message ----- > From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">uzunlarovunc at h...</A> > To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">myogananth at r...</A> , <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> > Date: Sat, 12 Apr 2003 18:13:44 -0100 > Subject: [oc] Can I get the time integrating correlator's [/q] verilog [q]> source code? > [q] > > > > > ----- Original Message ----- > From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">myogananth at r...</A> > To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">joe_zhao at s...</A> , <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> > Date: Sun, 2 Feb 2003 10:42:18 -0100 > Subject: Re: [oc] Can I get the sdram controller by FPGA? [/q] > (VHDL) [q] > [q]> > > > > > whether any project availble in low power [/q] dissipiation [q]> viterbi [q]> > decoder > > design using verilog > > > > > > > > > > > > > > > > ----- Original Message ----- > > From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">joe_zhao at s...</A> > > To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> > > Date: Tue, 26 Nov 2002 10:02:48 -0100 > > Subject: Re: [oc] Can I get the sdram controller by [/q] FPGA? [q] > (VHDL) [q]> > [q] > > > > > > I hope to get the sdram controller free core by [/q] FPGA [q] > (VHDL). [q] > > > > Joe zhao > > > > 11/26 > > ----- Original Message ----- > > From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">dheeraj_vij at r...</A> > > To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> > > Date: Thu, 10 Oct 2002 11:43:51 -0100 > > Subject: Re: [oc] Can I get the > > [q]> > > > > > > > > > > > > > > ----- Original Message ----- > > > From: "=?gb2312?B?sNe35g==?=" [/q] <<A HREF="http://www.opencores.org/mailman/listinfo/cores">baifeng at m...</A> [q] > [q]> > > To: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> > > > > Date: Tue, 5 Feb 2002 10:55:49 +0800 > > > Subject: Re: [oc] Can I get the "SDRAM [/q] > controller [q] > VHDL" [q]> > or [q] > > Verilog [q]> > > Source Code? > > > [q] > > > > > > > > > hai servan, > > > Can u send me the the source [/q] code [q]> of [q] > sdram [q] > > controller [q]> > > ? [q] > > > Thanks > > > baifeng > > > > > > ----- Original Message ----- > > > From: "I. Servan Uzun" <<A HREF="http://www.opencores.org/mailman/listinfo/cores">isu at b...</A> [/q] > [q] > > > To: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> > > > > Sent: Saturday, February 02, 2002 [/q] 7:53 PM [q] > > > Subject: Re: [oc] Can I get the [/q] "SDRAM [q] > controller [q]> > VHDL" [q] > > or [q]> > > Verilog [q] > > > Source Code? > > > > > > [q]> > > > Madhu, > > > > > > > > Below is the link for SDR SDRAM [/q] > Controller [q]> > Reference [q]> > > Design [q]> > > > [/q] > > > [/q] > > [/q] > <A HREF="http://www.altera.com/products/ip/altera/m-alt-sdr-sdram.shtml">http://www.altera.com/products/ip/altera/m-alt-sdr-sdram.shtml</A> [q]> > > > > > > > I didn' t searched for the [/q] source [q]> code but [q] > it [q]> > must [q] > > be [q] > > > somewhere on [q]> > > > the website. If you can not find [/q] it, [q]> I can [q] > send [q]> > VHDL [q]> > > source [q] > > > code to you [q]> > > > by e-mail. > > > > > > > > Regards, > > > > - Servan > > > > > > > > ----- Original Message ----- > > > > From: "Madhusudhan Rao" [/q] > > <<A HREF="http://www.opencores.org/mailman/listinfo/cores">madhu_sudhana_rao at y...</A> [q]> > > [q]> > > > To: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> > > > > > Sent: Friday, February 01, 2002 [/q] 11:23 [q]> PM [q]> > > > Subject: Re: [oc] Can I get the [/q] > "SDRAM [q]> > controller [q] > > VHDL" [q]> > > or [q] > > > Verilog Source [q]> > > > Code? > > > > > > > > [q] > > > > hai servan, > > > > Can u give me the [/q] address [q]> link [q] > for [q]> > the [q] > > source [q] > > > > code. > > > > > > > > Thanks > > > > Madhu > > > > > > > > --- "I. Servan Uzun" [/q] > <<A HREF="http://www.opencores.org/mailman/listinfo/cores">isu at b...</A> [q]> > > > wrote: [q]> > > > > Altera has a SDRAM [/q] > controller [q]> > megacore [q] > > function [q]> > > with [q]> > > > > an application note. I > > > > > have > > > > > used it with APEX20KE [/q] > device at [q]> > 100MHz. [q] > > Source [q]> > > code [q]> > > > > of the core is also > > > > > available in VHDL > > > > > on its website. > > > > > > > > > > - Servan > > > > > > > > > > ----- Original Message [/q] > ----- [q]> > > > > From: "sphuynh" [/q] > <<A HREF="http://www.opencores.org/mailman/listinfo/cores">sphuynh at m...</A> [q]> > [q]> > > > > To: <<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> [/q] > [q]> > > > > Sent: Thursday, [/q] January 31, [q]> 2002 [q] > 6:29 [q]> > PM [q]> > > > > Subject: RE: [oc] Can [/q] I get [q]> the [q]> > "SDRAM [q]> > > controller [q]> > > > > VHDL" or Verilog [/q] Source [q]> > > > > Code? > > > > > > > > > > [q] > > > > > Xilinx have a [/q] couple [q] > application [q] > > notes and [q] > > > source [q]> > > > > codes for SDRAM > > > > > controller [q] > > > > > for their Virtex [/q] and [q] > Spartan [q]> > family. [q] > > I'm [q]> > > not [q] > > > sure [q]> > > > > if this any useful to [q] > > > > > you. Below are [/q] the [q]> links. [q] > > > > > > > > > > DDR SDRAM [/q] controller: [q] > > > > > [/q] > > <A HREF="http://www.xilinx.com/xapp/xapp200.pdf">http://www.xilinx.com/xapp/xapp200.pdf</A> [q] > > > > > > > > > > SDR SDRAM [/q] controller: [q] > > > > > [/q] > > <A HREF="http://www.xilinx.com/xapp/xapp134.pdf">http://www.xilinx.com/xapp/xapp134.pdf</A> [q] > > > > > > > > > > Son Huynh > > > > > > > > > > > > > > > > > > > > -----Original [/q] > Message----- [q] > > > > > From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">hanz at c...</A> [/q] > > > > > [mailto:<A HREF="http://www.opencores.org/mailman/listinfo/cores">hanz at c...</A> ] [q] > > > > > Sent: Tuesday, [/q] January [q]> 29, [q] > 2002 [q]> > 1:15 [q] > > PM [q] > > > > > To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> > > > > > Subject: [oc] Can [/q] I [q]> get the [q]> > "SDRAM [q]> > > controller [q]> > > > > VHDL" or Verilog [/q] Source [q] > > > > > Code? > > > > > > > > > > > > > > > I'm a master [/q] source [q]> student [q] > in [q]> > KAIST. [q] > > > > > > > > > > I've been [/q] designed [q]> CMOS [q] > Digital [q] > > camera [q]> > > system, [q] > > > but [q]> > > > > I can't [q] > > > > > > > > > > realize SDRAM [/q] > controller [q] > using [q]> > Altera [q] > > Flex [q] > > > Chip. [q] > > > > > > > > > > Can I get the [/q] "SDRAM [q] > controller [q]> > VHDL" [q] > > or [q] > > > Verilog [q]> > > > > Source Code? [q] > > > > > > > > > > Thank you. > > > > > > > > > > > > > > > > > > > > -- > > > > > To unsubscribe [/q] from [q]> cores [q]> > mailing [q] > > list [q]> > > please [q]> > > > > visit [q] > > > > > [/q] > > > [/q] <A HREF="http://www.opencores.org/mailinglists.shtml">http://www.opencores.org/mailinglists.shtml</A> [q] > > > > > -- > > > > > To unsubscribe [/q] from [q]> cores [q]> > mailing [q] > > list [q]> > > please [q]> > > > > visit > > > > > [/q] > > <A HREF="http://www.opencores.org/mailinglists.shtml">http://www.opencores.org/mailinglists.shtml</A> [q] > > > > > [/q] > > > > > > > > > > > > > > > [/q] > > > > > > > > > > > > ===== > > > > MadhusudhanaRao.M > > > > > > > > > > > > [/q] > > > > > > > > > > > > [/q] > > > [/q] > > > [/q] > > [/q] > > [/q] > [/q] > [/q] [/q] ----- Original Message ----- From: mysticdude117 at y... To: cores at o... Date: Wed, 5 Nov 2003 15:40:41 +0100 Subject: Re: [oc] Can I get the time integrating correlator's verilog source code? ----- Original Message ----- From: sharma.amar at i... To: uzunlarovunc at h... , cores at o... Date: Fri, 12 Sep 2003 10:18:54 +0200 Subject: Re: [oc] Can I get the time integrating correlator's verilog source code? > > > > > ----- Original Message ----- > From: uzunlarovunc at h... > To: myogananth at r... , cores at o... > Date: Sat, 12 Apr 2003 18:13:44 -0100 > Subject: [oc] Can I get the time integrating correlator's verilog > source code? > > > > > > ----- Original Message ----- > From: myogananth at r... > To: joe_zhao at s... , cores at o... > Date: Sun, 2 Feb 2003 10:42:18 -0100 > Subject: Re: [oc] Can I get the sdram controller by FPGA? > (VHDL) > > > > > > > whether any project availble in low power dissipiation > viterbi > > decoder > > design using verilog > > > > > > > > > > > > > > > > ----- Original Message ----- > > From: joe_zhao at s... > > To: cores at o... > > Date: Tue, 26 Nov 2002 10:02:48 -0100 > > Subject: Re: [oc] Can I get the sdram controller by FPGA? > (VHDL) > > > > > > > > I hope to get the sdram controller free core by FPGA > (VHDL). > > > > Joe zhao > > > > 11/26 > > ----- Original Message ----- > > From: dheeraj_vij at r... > > To: cores at o... > > Date: Thu, 10 Oct 2002 11:43:51 -0100 > > Subject: Re: [oc] Can I get the > > > > > > > > > > > > > > > > > ----- Original Message ----- > > > From: "=?gb2312?B?sNe35g==?=" baifeng at m... > > > > To: cores at o... > > > > Date: Tue, 5 Feb 2002 10:55:49 +0800 > > > Subject: Re: [oc] Can I get the "SDRAM > controller > VHDL" > > or > > Verilog > > > Source Code? > > > > > > > > > > > > hai servan, > > > Can u send me the the source code > of > sdram > > controller > > > ? > > > Thanks > > > baifeng > > > > > > ----- Original Message ----- > > > From: "I. Servan Uzun" isu at b... > > > > To: cores at o... > > > > Sent: Saturday, February 02, 2002 7:53 PM > > > Subject: Re: [oc] Can I get the "SDRAM > controller > > VHDL" > > or > > > Verilog > > > Source Code? > > > > > > > > > > Madhu, > > > > > > > > Below is the link for SDR SDRAM > Controller > > Reference > > > Design > > > > > > > > > > http://www.altera.com/products/ip/altera/m-alt-sdr-sdram.shtml > > > > > > > > I didn' t searched for the source > code but > it > > must > > be > > > somewhere on > > > > the website. If you can not find it, > I can > send > > VHDL > > > source > > > code to you > > > > by e-mail. > > > > > > > > Regards, > > > > - Servan > > > > > > > > ----- Original Message ----- > > > > From: "Madhusudhan Rao" > > madhu_sudhana_rao at y... > > > > > > > To: cores at o... > > > > > Sent: Friday, February 01, 2002 11:23 > PM > > > > Subject: Re: [oc] Can I get the > "SDRAM > > controller > > VHDL" > > > or > > > Verilog Source > > > > Code? > > > > > > > > > > > > hai servan, > > > > Can u give me the address > link > for > > the > > source > > > > code. > > > > > > > > Thanks > > > > Madhu > > > > > > > > --- "I. Servan Uzun" > isu at b... > > > > wrote: > > > > > Altera has a SDRAM > controller > > megacore > > function > > > with > > > > > an application note. I > > > > > have > > > > > used it with APEX20KE > device at > > 100MHz. > > Source > > > code > > > > > of the core is also > > > > > available in VHDL > > > > > on its website. > > > > > > > > > > - Servan > > > > > > > > > > ----- Original Message > ----- > > > > > From: "sphuynh" > sphuynh at m... > > > > > > > To: cores at o... > > > > > > Sent: Thursday, January 31, > 2002 > 6:29 > > PM > > > > > Subject: RE: [oc] Can I get > the > > "SDRAM > > > controller > > > > > VHDL" or Verilog Source > > > > > Code? > > > > > > > > > > > > > > > Xilinx have a couple > application > > notes and > > > source > > > > > codes for SDRAM > > > > > controller > > > > > for their Virtex and > Spartan > > family. > > I'm > > > not > > > sure > > > > > if this any useful to > > > > > you. Below are the > links. > > > > > > > > > > DDR SDRAM controller: > > > > > > > http://www.xilinx.com/xapp/xapp200.pdf > > > > > > > > > > SDR SDRAM controller: > > > > > > > http://www.xilinx.com/xapp/xapp134.pdf > > > > > > > > > > Son Huynh > > > > > > > > > > > > > > > > > > > > -----Original > Message----- > > > > > From: hanz at c... > > > > > [mailto:hanz at c... ] > > > > > Sent: Tuesday, January > 29, > 2002 > > 1:15 > > PM > > > > > To: cores at o... > > > > > Subject: [oc] Can I > get the > > "SDRAM > > > controller > > > > > VHDL" or Verilog Source > > > > > Code? > > > > > > > > > > > > > > > I'm a master source > student > in > > KAIST. > > > > > > > > > > I've been designed > CMOS > Digital > > camera > > > system, > > > but > > > > > I can't > > > > > > > > > > realize SDRAM > controller > using > > Altera > > Flex > > > Chip. > > > > > > > > > > Can I get the "SDRAM > controller > > VHDL" > > or > > > Verilog > > > > > Source Code? > > > > > > > > > > Thank you. > > > > > > > > > > > > > > > > > > > > -- > > > > > To unsubscribe from > cores > > mailing > > list > > > please > > > > > visit > > > > > > > > http://www.opencores.org/mailinglists.shtml > > > > > -- > > > > > To unsubscribe from > cores > > mailing > > list > > > please > > > > > visit > > > > > > > http://www.opencores.org/mailinglists.shtml > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > ===== > > > > MadhusudhanaRao.M > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >

Can I get the time integrating correlator's verilog source code? by Unknown on Dec 24, 2003			Not available!
respected sir i need the sdram controller source code in vhdl for my project if u have please mail me sachin shashikantrao pampattiwar respected sir i need the sdram controller source code in vhdl for my project if u have please mail me sachin shashikantrao pampattiwar

no use

no use

1/1

no use

no use

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.