Hello,

I am a beginning verilog programmer and was sucessful in simulating the
bcd to binary converter using altera quartus/max+. Could someone
describe me using example how I can simulate it successfully using the
inputs? This is how I tried. I kept ce_i to "1" all times. first posedge
reset="1" 3rd posedge start="1" .. and my data is always on the input
wires. I get a binary output of all 0's. please help. :(

Thanking you,
Wally R.