hi, i am new to vhdl so this question may be easy for you.my question is:inorder to debug a vhdl program i want to assign a value to a in port.my port declaration is:
DATA_I : in std_logic_vector(7 downto 0);

i use modelsim simulator, do you have any idea how to assign a value to in port, for debugging?
Regards.

The simplest way in modelsim is to use the "force" command. When you start the simulation, type this command in the console window, and it will display the syntax options, or you can right click on the signal in the wave viewer and choose "force" from the menu. Have fun!

Hi,

This is an easy task with ModelSim. You have two opportunities to generate input stimuli on a certain port. Use a VHDL testbench where you include the device under test (DUT). An other way of generating signals on a certain port is by using a macro file (do-file) in ModelSim. How to do so is described in detail in this tutorial:
http://www.tkt.cs.tut.fi/tools/public/tutorials/mentor/modelsim/getting_started/gsms.html

Best wishes,
Andreas

Follow Below Steps;

1. Make New tb_top.vhd file
2. Instance Your Module
3. use random directive for your module input or write initial block
Example :
initial
begin
DATA_I = 8'h0;
@(posedge clk);
DATA_I = 8'h1;
@(posedge clk);
DATA_I = 8'h2;
.
.
.
end

or

random_i = $random;
module_name rand(
.clk(clk),
.rst(rst),
.DATA_I(random_i)
);

I hope this will help.....let me know if you need more detail...
Regards,
Ravi

thanks rogerkoehler, hga3 and ravivlsiii, i see your solutions at the same time, i thought that the third one(ravivlsiii's solution) was easy for me and applied it, it worked like a charm.thanks all again.

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