I try to figure out how binary BCD conversion code works in the given project but i can figure it out .
So please if ant one can write the working of it.

A BCD accumulator is intialised to 0

An N-bit binary value is shifted left, MSB first, to the LSB of the BCD accumulator.

As each successive bit is shifted out of the binary value:
- the BCD accumulator is multiplied by 2
- the (new) LSB of the BCD accumulator is the bit shifted out of the binary value

BCD accumulation continues until all bits of the binary value have been shifted into the BCD accumulator.

The BCD accumulator consists of the combinatorial function bcd_asl and the register bcd_reg.

You failed to mention the part where digit_less is assigned digit - 5, and digit is compared to > 4. Since BCD is decimal, base 10, and binary is base 2, it seems like there might be a clue in that 10/2=5. I have not fully analyzed this core. Other BCD converters work in groups of 4 bits, dividing the binary number by 10 repeatedly and saving the remainder. It seems that this core implements a shortcut that works without division, but, as I said, I have not taken the time to completely figure out this one.

I am not getting logic behind subtracting by 5 also value of bcd_reg after first left shift.

Subtracting 5 prevents the post-multiplication (by 2) decimal digit value from overflowing (exceeding the value of 9).

Can you explain program in term of flow chart if its possible.

No, this requires significant expenditure of time and effort, and it's not my code to explain or understand.

Suggest you implement the code and simulate it yourself, or -- using a pencil and paper -- walk yourself through the operation using some small (e.g. 8-bit) example starting data value.

There is two ways for making this kind of conversion :
- a binary decounter associated with a BCD counter
- shift binary register associated with shift BCD register
The first is ineficient because it takes untill 256 clock events to convert 8 bits !
The second is more efficient : only 16 clock events for 16-bit register.

I have not completly read the verilog code but I suspect the conversion is a second type conversion. The problem of this conversion is to imagine a shift BCD register : a kind of register that keeps the beautiful property of multiplying per two when shift left. Draw a 3 digits BCD register and shift a lot of numbers in it and you will (re)discover the rules.

For your information this conversion is descibed in the P.P. Chu's book "FPGA prototyping with verilog"

Good luck for the investigation.