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AXI-to-Wishbone Bridge
by cassano on Jan 12, 2012
Posts: 1
Joined: Apr 28, 2009
Last seen: Oct 22, 2014
Hi everyone,

I know there exists a PLB-to-Wishbone bridge in cores, but PLB has become a legacy bus standard according to Xilinx tools and will not be supported starting with the 7-Series FPGA's. I think it is the same case for Altera also. Is there a AXI-to-Wishbone bridge project in planning?
RE: AXI-to-Wishbone Bridge
by refugee on Jul 20, 2012
Posts: 2
Joined: Mar 25, 2010
Last seen: Jul 22, 2020

really interesting post, I truly wonder why nobody else has referred to an AXI-WB Bridge so far.

FYI, I found some sort of implementation @ - I haven't yet had the chance to take a look at it, but it's a start nevertheless.

Would be nice if we kept in touch on any update regarding this particular issue! :-)

RE: AXI-to-Wishbone Bridge
by jorge.echavarria on Jun 9, 2015
Posts: 1
Joined: Sep 4, 2013
Last seen: Jun 26, 2019

I am really interested in this bridge, have you found anything yet?
RE: AXI-to-Wishbone Bridge
by dgisselq on Jun 9, 2015
Posts: 247
Joined: Feb 20, 2015
Last seen: Jul 15, 2022
Have you taken a look at Dan Strother's code at all yet? It looks like there's an AXI master to WB slave interface in there. Does that meet your needs?

RE: AXI-to-Wishbone Bridge
by brent.nolan on Sep 20, 2017
Posts: 3
Joined: Apr 22, 2016
Last seen: Jun 29, 2020
Here's links to two AXI to Wishbone implementations. One is on OpenCores and the other is Dan's 2011 implementation.

Dan Stother's code:

OpenCores AXI to WB Project by Adrian Byszuk and Wojciech Zabolotny:,ax4lbr
-- GitHub repo is at

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