Dear Jacob It is great to have this source code of "uart16550 core" on your page. Thanks for your hard work. I am trying to use this with SH4 CPU. I have a question and would like your advice. Your source code has only one clock which controlls every thing. And Baud rate can be set by the Divisor Latch Register. In my case, I have CPU bus clock of 100Mhz which can also be set to 25Mhz. And I have a 1.8432Mhz crystal on my board. On the CPU side for Rgisters settings in FPGA, I want to use 100Mhz clock or 25 MHz but for Serial side (baud rate) I want to use the 1.8432Mhz crystal. And then the Baud rate Reg will set to value based on 1.8432Mhz . Would you please tell which internal signal in uart source code should I connect to this 1.8432Mhz crystal. Thanks and regards. Hadi Yokohama, Japan ******************************************** *------------------------------------------* BRAINS Corporation N. Hadi Tamagawa Business Park 4F 2-27-8 Tamagawa, Setagaya-ku, Tokyo 158-0094, Japan. TEL:03-3708-8761 FAX:03-5717-7172 email: hadi at brains.co.jp http://www.brains.co.jp *------------------------------------------* ******************************************** -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums.cgi/cores/attachments/20041119/05145624/attachment.htm