I have ported the 'uart16550' core for use with the Altera Nios II
processor. This involved replacing the WISHBONE bus interface with an
Altera Avalon bus interface - essentially removing the uart_wb.v file,
changing some signal names, and using the 8-bit data bus.

I am using the core with some existing code that was driving a 16C752, with
some minor modifications to eliminate 16750-specific features such as
Auto-RTS and programmable Tx / Rx interrupt trigger levels. The issue I saw
was an immediate Timeout interrupt, but with no characters present in the Rx
FIFO. Given the ISR logic I use, the ISR never returns - I don't read from
the RHR unless there is something in the FIFO (as reported by the LSR).

Perhaps other code works "properly", but I believe only by coincidence. I
believe a bug fix to the ti_int signal is required for 16x50-compatible
behavior. I changed line 753 of uart_regs.v from:

assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0);

to:

assign ti_int = ier[`UART_IE_RDA] && (|rf_count) && (counter_t == 10'b0);

This makes sense, since there shouldn't be a timeout interrupt unless the Rx
FIFO has at least one character in it. Could one of the IP core maintainers
comment on the correctness of this bug fix? I am now completely happy with
the uart16550 core, but I wanted to share this change with the community...

Thank you,
Joe Bruce

Hi, Joe. Looks like you're right. I did the change and commit it to the opencores. Thanks for the report. Best regards, Igor On Sun, 21 Nov 2004 11:24:07 -0500, Joe Bruce psujobu at hotmail.com> wrote:

Joe, I am attempting to port the USB 1.1 core, also to the Avalon bus. Would you be willing to share your modified core so that I may see your interface? Regards, Dalton ----- Original Message ----- From: Joe Brucepsujobu at h...> To: Date: Sun Nov 21 17:24:07 CET 2004 Subject: [oc] Bug / Bug Fix: uart16550 timeout interrupt

Hi, Dalton, Unfortunately I cannot provide the entire SOPC Builder component. However, I have attached a gzip'ed context diff (suitable for use with 'patch', which is included with the Altera Nios II SDK) that contains the changes to the Verilog code. From that point, you simply import the Verilog into SOPC Builder via the "Interface to User Logic" component - see AN333 for detailed instructions. That portion of the work only takes about 15-30 minutes, and the whole port took 5 hours. Note that in my own version, I renamed "wb_*" to "avalon_*". I changed the names back in order to generate a more concise diff. Also note that a couple changes were made based upon warnings during synthesis (e.g., unused wire 'rbit_in'). I didn't bother porting the 32-bit interface -- I only made the 8-bit interface (8 bits per every 32 bits of address space) work. Finally, note that I do not register the Avalon signals, as the majority are already registered. Perhaps this is a poor design choice on my part - I have about four weeks of Verilog experience on top of 10+ years as an embedded software engineer. In other words, this comes with even less of a "no warranty" than the uart16550 core. ;-) FYI, in my Cyclone-based design, each instance of the UART consumes approximately 1K LEs and zero memory bits. Regards, Joe ----Original Message Follows---- From: dmarris at charter.net Reply-To: Discussion list about free open source IP cores cores at opencores.org> To: cores at opencores.org Subject: Re: [oc] Bug / Bug Fix: uart16550 timeout interrupt Date: Fri, 26 Nov 2004 18:58:19 +0100 Joe, I am attempting to port the USB 1.1 core, also to the Avalon bus. Would you be willing to share your modified core so that I may see your interface? Regards, Dalton ----- Original Message ----- From: Joe Brucepsujobu at h...> To: Date: Sun Nov 21 17:24:07 CET 2004 Subject: [oc] Bug / Bug Fix: uart16550 timeout interrupt > I have ported the 'uart16550' core for use with the Altera Nios II > processor. This involved replacing the WISHBONE bus interface with > an > Altera Avalon bus interface - essentially removing the uart_wb.v > file, > changing some signal names, and using the 8-bit data bus. > I am using the core with some existing code that was driving a > 16C752, with > some minor modifications to eliminate 16750-specific features such > as > Auto-RTS and programmable Tx / Rx interrupt trigger levels. The > issue I saw > was an immediate Timeout interrupt, but with no characters present > in the Rx > FIFO. Given the ISR logic I use, the ISR never returns - I don't > read from > the RHR unless there is something in the FIFO (as reported by the > LSR). > Perhaps other code works "properly", but I believe only > by coincidence. I > believe a bug fix to the ti_int signal is required for > 16x50-compatible > behavior. I changed line 753 of uart_regs.v from: > assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0); > to: > assign ti_int = ier[`UART_IE_RDA] && (|rf_count) && > (counter_t == 10'b0); > This makes sense, since there shouldn't be a timeout interrupt > unless the Rx > FIFO has at least one character in it. Could one of the IP core > maintainers > comment on the correctness of this bug fix? I am now completely > happy with > the uart16550 core, but I wanted to share this change with the > community... > Thank you, > Joe Bruce > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores -------------- next part -------------- A non-text attachment was scrubbed... Name: avalon.diff.gz Type: application/x-gzip Size: 2462 bytes Desc: not available Url : http://www.opencores.org/forums.cgi/cores/attachments/20041201/35d666b1/avalon.diff.bin